emc163sp16k Emlsi Inc., emc163sp16k Datasheet - Page 13

• Manufacturer Part Number: emc163sp16k
• Description: 1mx16 Bit Cellularram Ad-mux
• Manufacturer: Emlsi Inc.

Figure 6: Burst Mode WRITE (4-word burst, OE# HIGH)
Note: Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency;
latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen,
or thirty-two words. Continuous bursts have the ability to start at a specified address and burst to the end of the address. It goes back to
the first address and continues to burst when continuous bursts meet the end of address.
The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between
the processor and CellularRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE
operations always use fixed latency). Variable latency allows the CellularRAM to be configured for minimum latency at high clock
frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles.
Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency
time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency
also provides improved performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of ) the memory.
WAIT will again be asserted at the boundary of the row, unless wrapping within the burst length. With wrap off, the CellularRAM device
will restore the previous row’s data and access the next row, WAIT will be de-asserted, and the burst can continue across the row
boundary(See Figure 29 for a READ, Figure 34 for a WRITE). If the burst is to terminate at the row boundary, CE# must go HIGH within
2 clocks of the last data(See Figure 28). CE# must go HIGH before any clock edge following the last word of a defined-length burst
WRITE(See Figure 31 and 32).
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than t
to remain LOW for longer than t
A/DQ[15:0]
LB#/UB#
A[19:16]
ADV#
WAIT
WE#
CLK
CE#
WRITE Burst Identified
(WE# = LOW)
Address
Address
CEM
Latency Code 2(3 clocks)
, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle.
D0
D1
D2
13
D3
WRITE Burst Identified
(WE# = LOW)
1Mx16 CellularRAM AD-MUX
CEM
Address
Address
. If a burst suspension will cause CE#
EMC163SP16K
Don’t Care