emc163sp16k Emlsi Inc., emc163sp16k Datasheet - Page 45

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emc163sp16k

Manufacturer Part Number
emc163sp16k
Description
1mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
Figure 32: Burst WRITE Operation - Fixed Latency Mode
Note:
1. Nondefault BCR settings for burst WRITE operation in fixed latency mode: fixed latency, latency code 2(3 clocks), WAIT active LOW,
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
3.
4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
WAIT asserted during delay, burst length 4, burst wrap enabled.
t
AS required if
A/DQ[15:0]
UB#/LB#
A[19:16]
ADV#
WAIT
WE#
CLK
CE#
OE#
t
CSP > 20ns.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
t
t
t
AS
AS
AS
High-Z
3
3
3
WRITE Burst Identified
(WE# = LOW)
t
t
t
t
SP
SP
CSP
Valid Address
SP
t
Valid Address
SP
t
KHTL
t
t
HD
HD
t
AVH
t
AVH
Note2
45
t
KHTL
t
t
KOH
SP
t
CLK
t
CEM
t
SP
D1
t
HD
t
HD
t
KHKL
D2
1Mx16 CellularRAM AD-MUX
D3
t
KP
EMC163SP16K
t
KP
D0
t
HD
Don’t Care
t
HZ
t
Note 4
CBPH
High-Z

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