emc163sp16k Emlsi Inc., emc163sp16k Datasheet - Page 26

• Manufacturer Part Number: emc163sp16k
• Description: 1mx16 Bit Cellularram Ad-mux
• Manufacturer: Emlsi Inc.

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to
valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous
READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the
de-asserted or asserted state, respectively. When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going
valid or invalid(See Figure 16).
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT
signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
Figure 16: WAIT Configuration During Burst Operation
Note: Non-default BCR setting: WAIT active LOW.
Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data
value transferred. For allowable latency codes, see Table 5 and 6 on pages 26 and 27, respectively, and Figure 17 and 18 in page 27,
respectively.
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to
detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that
allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is
not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency
counter(See Table 6 on page 27 and Figure 18 on page 27).
Table 5: Variable Latency Configuration Codes
Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
BCR[13:11]
Others
010
011
100
2 (3 clocks)
3 (4 clocks)-default
4 (5 clocks)
Reserved
Configuration
A/DQ[15:0]
Latency
Code
WAIT
WAIT
CLK
initial latency
Normal
2
3
4
-
D0
Latency 1
D1
Refresh Collision
26
D2
4
6
8
-
D3
End of row
104(9.62ns) 104(9.62ns)
133(7.5ns)
66(15ns)
Max Input CLK Frequency (MHz)
133
1Mx16 CellularRAM AD-MUX
-
Don’t Care
BCR[8] = 1
Data Valid in next cycle
BCR[8] = 0
Data Valid in current cycle
EMC163SP16K
66(15ns)
104
-
-
52(19.2ns)
83(12ns)
83
-
-