EMD28164PA Emlsi Inc., EMD28164PA Datasheet
EMD28164PA
Related parts for EMD28164PA
EMD28164PA Summary of contents
Page 1
... Signal names unified to /CK, /CS, /RAS, /CAS, /WE respectively (Ex.) CK#, CK, CKB unified to /CK - Corrected IDD6 value in Table 16 Release - Table 6 DC CHARACTERISTICS updated for IDD3P, IDD3N, IDD6 - Table 8 OPERATING AC PARAMETER updated for tDS, tDH, tQH, tRC Homepage : www.emlsi.com 1 EMD28164PA 128M Mobile DDR SDRAM Rev 1.0 ...
Page 2
... Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. GENERAL DESCRIPTION This EMD28164PA is 134,217,728 bits synchronous double data rate Dynamic RAM. Each 33,554,432 bits bank is organized as 4,096 rows by 512 columns by 16 bits, fabricated with EMLSI’s high performance CMOS technology ...
Page 3
... Used to capture write data. For x16 device, LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to the data on DQ8-DQ15. VDD Supply Power Supply VSS Supply Ground VDDQ Supply I/O Power Supply VSSQ Supply I/O Ground EMD28164PA 128M Mobile DDR SDRAM Descriptions 3 Rev 1.0 ...
Page 4
... PRE PRE Precharge PREALL EMRS = Ext. Mode Reg. Set MRS = Mode Register Set PRE = Precharge PREALL = Precharge All Banks REFA = Auto Refresh REFS = Enter Self Refresh 4 EMD28164PA 128M Mobile DDR SDRAM Self Refresh Auto REFA Refresh Precharge Power Down Burst ...
Page 5
... EXTENDED MODE ○ REGISTER /WE BANK MEMORY ARRAY 4,096 (4,096 x 256 x 32 SENSE AMPLIFIERS 32 256 COLUMN - 32 I/O GATING ADDRESS DM MASK LOGIC DECODER EMD28164PA 128M Mobile DDR SDRAM DQS 2 2 GENERATOR DQS DRIVER Dout Dout Parallel DRIVER to Serial Din 16 16 Din Serial INPUT BUF ...
Page 6
... V 0 DDQ 1.8V 1.8V 25℃, f=1㎒) DD DDQ A Symbol C IN1 C IN2 C out C IN3 6 EMD28164PA 128M Mobile DDR SDRAM Value -0.5 ~ 2.5 -0.5 ~ 2.5 -55 ~ +150 1 for Extended) Max Unit 1. 0.3 V DDQ 0 0 DDQ ㎂ 2 ㎂ 5 Min ...
Page 7
... HIGH; Extended Mode Reg- ister set to all 0s; address and control inputs are STABLE; 1/2 of Full Array data bus inputs are STABLE 1/4 of Full Array Address and Control inputs are STABLE; data bus inputs are STABLE 7 EMD28164PA 128M Mobile DDR SDRAM Version -60 - ...
Page 8
... V 0.4 × V (Min) / 0.6 × V DDQ See Figure 2 (DC) = 0.9 × -0.1㎃ DDQ OH (DC) = 0.1 × 0.1 ㎃ DDQ OL Output 8 EMD28164PA 128M Mobile DDR SDRAM Unit V DDQ V DDQ V/㎱ V DDQ (Max) V DDQ Vtt=0.5 × V 50Ω Z0=50Ω 20㎊ Figure 2. AC Output Load Circuit ...
Page 9
... IPW t 1 0.5 DQSQ QHS t 0.65 QHS t 1.25 0.75 DQSS t 0.6 0.4 DQSH t 0.6 0.4 DQSL t 0.2 DSS t 0.2 DSH t 2 MRD t 0 WPRES t 0.6 0.4 WPST t 0.25 WPRE 9 EMD28164PA 128M Mobile DDR SDRAM -75 -90 Min Max Min Max 2.5 6.0 2.5 7.0 2.5 6.0 2.5 7.0 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 min min ( 7.5 100 9 100 12 100 15 100 1.0 0.75 1.0 0.75 2.0 1.8 1.5 1 ...
Page 10
... WTR t 120 XSR CKE t 64 REF ∆t IS (ps) 0 +50 +100 in the case where the input slew rate is below 1.0V/ns. IH and minimum 3CK for EMD28164PA 128M Mobile DDR SDRAM -75 -90 Min Max Min Max 1.1 0.5 1.1 0.5 1.1 0.9 1.1 0.9 0.6 0.4 0.6 0.4 45 100,000 54 100,000 67 ...
Page 11
... I/O slew rate is below 1.0V/ns. DH ∆t DS (ps) 0 +50 +100 /t in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated EMD28164PA 128M Mobile DDR SDRAM ∆t DH (ps) 0 +75 +150 ∆t DH (ps) 0 +50 +100 Rev 1 ...
Page 12
... Note that the sequence in which the standard and extended mode registers are programmed is not critical. 10. Issue NOP or DESELECT commands for at least tMRD time. 11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command. EMD28164PA 128M Mobile DDR SDRAM 12 ...
Page 13
... A0-A6 set to the desired values. All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. EMD28164PA 128M Mobile DDR SDRAM 13 ...
Page 14
... This will eliminate timing violations that may otherwise occur during normal operational accesses. 128M Mobile DDR SDRAM BA1=0 BA1=0 BA1=0 BA0=0 BA0=1 BA0=0 BA0=1 BA1=1 BA1=1 BA1=1 BA0=0 BA0=1 BA0=0 BA0=1 - 1/4 Array - 1/2 Array 14 EMD28164PA Partial Self Refresh Area BA1=0 BA1=1 Rev 1.0 ...
Page 15
... Reserved Reserved Reserved Mode Register Set * Clock min EMD28164PA 128M Mobile DDR SDRAM CAS Latency BT Burst Length Burst Type Burst Length Type A2 A1 Sequential 0 0 Interleave 0 0 Mode Select 0 1 BA0 ...
Page 16
... Driver Strength Driver A6 A5 Strength 0 0 Full 1/8 Self Refresh Current (I 1/2 of Full Array 200 160 150 120 16 EMD28164PA 128M Mobile DDR SDRAM RFU PASR Size of Refreshed Array Full Array 1/2 of Full Array 0 ...
Page 17
... EMD28164PA 128M Mobile DDR SDRAM Interleave 0 1 Interleave Interleave ...
Page 18
... EMD28164PA 128M Mobile DDR SDRAM Interleave ...
Page 19
... READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state the pre- viously open row is already in the process of precharging. EMD28164PA 128M Mobile DDR SDRAM 19 ...
Page 20
... The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later. Auto Refresh /CK CK Command PRE CKE = High t RP Auto Refresh t RFC 20 EMD28164PA 128M Mobile DDR SDRAM CMD Rev 1.0 ...
Page 21
... This mode is entered by having all banks idle then edge of the clock, while CKE is LOW. This mode is exited by asserting CKE HIGH. 128M Mobile DDR SDRAM t IS and /WE held LOW with /RAS and /CAS held HIGH at the rising /CS 21 EMD28164PA Active CMD t XSR Rev 1.0 ...
Page 22
... Bank A Command NOP Activate Bank A Col. Addr. ) RCD Write NOP with Auto Precharge Row Cycle Time(tRC) 22 EMD28164PA 128M Mobile DDR SDRAM Tn Tn+1 Tn+2 Bank B Bank A Row Addr. Row. Addr. RAS - RAS delay time(t ) RRD Bank B Bank A NOP Activate Activate : Don't care ...
Page 23
... Burst Read Operation < Burst Length=4, CAS Latency=2, 3) > /CK CK Command NOP READ t RPRE DQS CL2 DQ’s DQS CL3 DQ’ NOP NOP NOP t RPST Dout 0 Dout 1 Dout 2 Dout 3 t RPRE Dout 0 Dout 1 Dout 2 Dout 3 23 EMD28164PA 128M Mobile DDR SDRAM NOP NOP NOP 8 NOP Rev 1.0 ...
Page 24
... NOP WRITE NOP Dout 0 Dout 1 Din 0 Din NOP NOP NOP Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 Interrupted by precharge 24 EMD28164PA 128M Mobile DDR SDRAM NOP NOP NOP NOP NOP NOP Din 2 Din NOP ...
Page 25
... Burst Write Operation < Burst Length=4 > /CK CK Command WRITE A NOP DQS t t DSH WPRES DQ’ NOP WRITE B NOP t DQSSmax t DSS Din a0 Din a1 Din a2 Din a3 Din b0 Din b1 Din b2 Din b3 25 EMD28164PA 128M Mobile DDR SDRAM NOP NOP NOP 8 NOP Rev 1.0 ...
Page 26
... DSS t WPRE Din 0 Din 1 Din 2 Din 3 Din DSS t WPRE Din 2 Din 0 Din 1 Din 3 Din 4 Din 5 26 EMD28164PA 128M Mobile DDR SDRAM NOP NOP NOP NOP READ NOP WTR Din 7 Dout 0 Dout 1 Dout 2 Dout 3 Din 5 Din 6 WTR Din 6 ...
Page 27
... NOP NOP NOP The burst ends after a delay equal to the CAS latency. Dout0 Dout1 Dout0 Dout1 NOP NOP NOP Din 4 Din 5 Din 6 Din EMD28164PA 128M Mobile DDR SDRAM Precharge A NOP WRITE B t DQSSmax DQSSmin Din b0 Din b1 ...
Page 28
... NOP NOP Auto Precharge t RAS(min.) Begin Auto-Precharge WRITE NOP NOP NOP Auto Precharge Din 0 Din 1 Din 2 Din 3 28 EMD28164PA 128M Mobile DDR SDRAM NOP NOP NOP Dout0 Dout1 Dout2 Dout3 Dout0 Dout1 Dout2 Dout3 ...
Page 29
... NOP or DESELECT command). NOPs or DESELECT commands must be maintained on the command bus until t is satisfied. Power down /CK CK Precharge Command Precharge CKE = High power down Entry 29 EMD28164PA 128M Mobile DDR SDRAM Active Active power power Active down down Entry Exit t IS ...
Page 30
... after the end of burst EMD28164PA 128M Mobile DDR SDRAM /CAS /WE BA0,1 A10/ CODE Row Address ...
Page 31
... HIGH BAa DISABLE AUTO PRECHARGE Ca t RPRE Qa0 Qa1 Qa2 Qa3 READ t RPST DQS EMD28164PA 128M Mobile DDR SDRAM BAb DISABLE AUTO PRECHARGE DQSS DSC Hi-Z RPST WPRE DQSL ...
Page 32
... DQS DQ DM COMMAND ACTIVE HIGH BAb BAa Rb DISABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE Rb Ca Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 ACTIVE READ 32 EMD28164PA 128M Mobile DDR SDRAM BAb Cb READ 10 Rev 1.0 ...
Page 33
... DQ DM COMMAND ACTIVE HIGH BAb BAa Rb DISABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE Rb Ca Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 t RCD ACTIVE WRITE WRITE 33 EMD28164PA 128M Mobile DDR SDRAM BAb Cb 10 Rev 1.0 ...
Page 34
... The new read/write command of another activated bank can be issued from this point At burst read/write with auto precharge, CAS interrupt of the same is illegal HIGH Auto Precharge start(Note 1) Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 34 EMD28164PA 128M Mobile DDR SDRAM BAa ACTIVE Rev 1.0 10 ...
Page 35
... The new read/write command of another activated bank can be issued from this point At burst read/write with auto precharge, CAS interrupt of the same bank/another bank is illegal HIGH 35 EMD28164PA 128M Mobile DDR SDRAM Auto Precharge start(Note DAL ACTIVE Rev 1 ...
Page 36
... CKE /CS /RAS /CAS BA0,BA1 BAa A10/AP DISABLE AUTO PRECHARGE ADDR Ca (A0-A9,A11) /WE DQS Da0 Da1 Da2 Da3 DQ DM COMMAND WRITE HIGH BAa SINGLE BANK t WR PRE CHARGE 36 EMD28164PA 128M Mobile DDR SDRAM Rev 1.0 10 ...
Page 37
... Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 DQ DM COMMAND WRITE HIGH BAa SINGLE BANK DISABLE AUTO PRECHARGE PRE WRITE CHARGE 37 EMD28164PA 128M Mobile DDR SDRAM BAb BAc Cb Cc Db0 Db1 Dc0 Dc1 Dc2 Dc3 Dc4 Dc5 t CCD WRITE 10 Rev 1.0 ...
Page 38
... ADDR Ca (A0-A9,A11) /WE DQS DQ DM COMMAND WRITE HIGH BAb DISABLE AUTO PRECHARGE Cb Da0 Da1 Da2 Da3 Da4 Da5 t WTR READ 38 EMD28164PA 128M Mobile DDR SDRAM Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 Rev 1.0 10 ...
Page 39
... A new Bank Activate command may be issued to the same bank after tRP HIGH BAa ALL BANK 2 t valid CK Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 PRE CHARGE 39 EMD28164PA 128M Mobile DDR SDRAM Rev 1.0 10 ...
Page 40
... DISABLE AUTO PRECHARGE ADDR Ca (A0-A9,A11) /WE DQS DQ DM COMMAND READ HIGH BAb DISABLE AUTO PRECHARGE Cb Qa0 Qa1 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7 Burst WRITE stop 40 EMD28164PA 128M Mobile DDR SDRAM Rev 1.0 10 ...
Page 41
... BA0,BA1 BAa A10/AP DISABLE AUTO PRECHARGE ADDR Ca (A0-A9,A11) /WE DQS DQ DM COMMAND READ HIGH BAb Cb Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 t CCD READ 41 EMD28164PA 128M Mobile DDR SDRAM Qb6 Qb7 Rev 1.0 10 ...
Page 42
... DM Function (@BL=8) only for write /CK CKE /CS /RAS /CAS BA0,BA1 BAa A10/AP DISABLE AUTO PRECHARGE ADDR Ca (A0-A9,A11) /WE DQS DQ DM COMMAND WRITE HIGH Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 42 EMD28164PA 128M Mobile DDR SDRAM Rev 1.0 10 ...
Page 43
... NOPs or DESELECTs are required during this time NOP NOP PRE AR 4 T=200us RFC and CK stable 43 EMD28164PA 128M Mobile DDR SDRAM ACT AR MRS EMRS CODE CODE CODE CODE BA0=L ...
Page 44
... DQS Precharge Command All Bank Note 1 Power & Clock must be stable for 200us before precharge all banks HIGH 2 Clock min Any Command Mode Register Set Command 44 EMD28164PA 128M Mobile DDR SDRAM Rev 1.0 10 ...
Page 45
... Bank 2 ----------------------- 2 Bank 4 ----------------------- 4 Bank 6. Interface ( VDD,VDDQ ) V ------------------------- LVTTL ( 3.3V,3.3V ) H------------------------- LVTTL ( 3.3V,2. ------------------------- LVTTL ( 3.0V,3. ------------------------- LVTTL ( 3.0V,2. ------------------------- P-LVTTL ( 3.0V,1. ------------------------- LVCMOS ( 2.5V,2. ------------------------- LVCMOS ( 2.5V,1. ------------------------- LVCMOS ( 1.8V,1.8V ) EMD28164PA 128M Mobile DDR SDRAM 11. Temperature 7. Version Blank ----------------- 1st generation A ------------------------2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation 8. Package Blank ----------------- KGD U ------------------------44 TSOP2 P ----------------------- 48 FpBGA ...