emc163sp16k Emlsi Inc., emc163sp16k Datasheet - Page 14

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emc163sp16k

Manufacturer Part Number
emc163sp16k
Description
1mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
Figure 7: Refresh Collision During Variable-Latency READ Operation
Note: Non-default BCR settings for refresh collision during variable-latency READ operation:
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
A/DQ[15:0]
LB#/UB#
A[19:16]
ADV#
WAIT
WE#
CE#
OE#
CLK
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
OH
OH
IH
OL
OL
IL
IH
IH
IL
IH
IH
IH
IL
IL
IL
IL
IL
Additional WAIT states inserted to allow refresh completion.
High-Z
Address
Address
Valid
Valid
V
V
OH
OL
14
D0
D1
1Mx16 CellularRAM AD-MUX
Don’t Care
D2
D3
EMC163SP16K
Undefined

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