peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 97

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

4.7.2.5
Due to signalling procedures, the E-bits of frame 13 and frame 15 of the CRC-4
multiframe can be used to indicate received errored submultiframes:
no CRC error : E = ’1’
CRC error
Standard Procedure
E-bits of the service word are replaced by values of bit XSP.XS13 and XSP.XS15.
Automatic Procedure
Values programmed in register Status information of received submultiframes is
automatically inserted in E-bit position of the outgoing CRC-4 Multiframe without any
further interventions of the microprocessor.
In the double- and multiframe asynchronous state the E-bits are set to zero. In the
multiframe synchronous state the E-bits are processed according to ITU-T G.704.
Submultiframe Error Indication Counter
The Error Bit Counter counts zeros in E-bit position of frame 13 and 15 of every received
CRC-4 multiframe. This counter option gives information about the outgoing transmit line
if the E-bits are used by the remote end for submultiframe error indication. Incrementing
is only possible in the multiframe synchronous state.
The S
sequence 0010
in every submultiframe on a selectable S
CRC errors detected at T-reference points are reported via S
possible in the multiframe synchronous state.
Data Sheet
a
-bit error indication counter CRC2 (16 bits) counts either the received bit
E-Bit Access
B
: E = ’0’
and 0011
B
or two user programmable values defined in register VCRC
a
-bit. In the primary rate access digital section
97
Functional Description
a6
. Incrementing is only
PEB 3456 E
05.2001