peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 76

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

programmed to either flag 7E
In receive operation, prior to Frame check sum (FCS) computation, any ‘0’ bit that
directly follows five contiguous ‘1’ bits is discarded. When closing flag is recognized, a
CRC check, octet boundary check, MFL (maximum frame length) check, a short frame
check and an additional small frame check are performed. Short frames have less than
4 octets if CRC16 is used or less than 6 octets if CRC32 is used. An aborted frame is
recognized if 7 or more ‘1’s are received.
In transmit operation after the CRC computation a ‘0’ bit is inserted after every sequence
of five contiguous ‘1’ bits. When frame end is indicated in the belonging transmit
descriptor the calculated CRC is transmitted and a flag is generated. If an underrun
• As long as the amount of data stored in the transmit buffer is below the transmit refill
Note: Since there is a delay between the time the transmit buffer requests data from the
4.5
The protocol machines provide protocol handling for up to 256 channels. The protocol
machines implement 4 modes, which can be programmed independently for each
channel: HDLC, bit-synchronous PPP, octet-synchronous PPP and transparent mode A.
The configuration of each logical channel is programmed via the PCI bus and will be
stored inside the protocol machines. Furthermore the current state for the protocol
processing (CRC check, 1 bit count,...) is also stored inside the protocol machines.
Each protocol machine (receive, transmit) handles a maximum of 256 channels and a
maximum aggregate bit rate of up to 45 Mbit/s.
4.5.1
•
Figure 4-9
The frame begin and frame end synchronization is performed with the flag character
7E
programmed in the channel configuration register for transmit direction. Shared ‘0’ bit
between two flags is only supported in receive direction. Interframe time-fill can be
Data Sheet
threshold the data management unit will keep filling the buffer by initiating PCI burst
transfers.
H
0111 1110
. Shared opening and closing flag is supported in receive direction and can be
data management unit and the time the data management unit serves the request,
the actual number of empty locations may be higher than the transmit refill
threshold. To determine the maximum PCI burst length an additional parameter is
available which limits these requests up to a maximum of 64 DWORDs.
Flag
Protocol Description
HDLC Mode
HDLC Frame Format
Address
8 bits
H
or FF
Control
8 bits
H
indicating idle.
76
Information
<=0 Bits
16/32 bits
Functional Description
CRC
PEB 3456 E
0111 1110
Flag
05.2001