peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 50

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Data management units
The data management units provide direct data transfer between the system memory
and the internal buffers. Each channel has an associated linked list of descriptors, which
is located in system memory and handled by the data management units. This linked list
is the interface between the system processor and the TE3-CHATT for exchange of data
packets. The descriptors and the data packets can be stored arbitrarily in 32 bit address
space of system memory, thus allowing full scatter/gather assembly of packets. In order
to optimize PCI bus utilization, each descriptor is read in one burst and held on-chip
afterwards.
Interrupt controller
Two interrupt controllers manage internal interrupts. Interrupts from the mailbox, the
framing engines and the signalling controller are passed in the form of interrupt vectors
to an internal interrupt FIFO which can be read from the local bus. All system, port and
channel related interrupt information is passed to the main interrupt controller which is
connected to the PCI system. A programmable DMA with nine channels stores these
interrupts in the form of interrupt vectors in different interrupt queues in system memory.
PCI interface
The PCI interface unit combines all DMA requests from the internal data management
unit and the interrupt controller and translates them into PCI Rev. 2.1 compliant bus
accesses. The PCI interface optionally includes the function of loading the subsystem
vendor ID and the subsystem ID from an external SPI compliant EEPROM.
Mailbox, internal bridge and global registers
The mailbox is used to exchange data between the PCI attached microprocessor and
the local bus microprocessor and provides a doorbell function between the two
interfaces.
Controlled by an arbiter an internal bridge connects the configuration bus I and the
configuration bus II. It is therefore possible to access the “layer one” registers from the
Internal buffer
The internal buffers provides channelwise buffering of raw (unformatted/deformatted)
data for 256 logical channels. Channel specific thresholds can be programmed
independently in transmit and receive direction. In order to avoid transmit underrun
conditions each transmit channel has two control parameters for smoothing the filling/
emptying process (transmit forward threshold, transmit refill threshold). In receive
direction each channel has a receive burst threshold. To avoid unnecessary waste of bus
bandwidth, e.g. in case of transmission errors, the receive buffer provides the capability
to discard frames which are smaller than a programmable threshold.
Data Sheet
50
General Overview
PEB 3456 E
05.2001