peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 278
peb3456
Manufacturer Part Number
peb3456
Description
Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456.pdf
(424 pages)
- Current page: 278 of 424
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IRD
URD
FFM
IRCK
Data Sheet
F Framing Mode
This bit selects the F-bit error condition which triggers the DS3 framer to
start a new frame search.
0
1
Invert Receive Clock
This bit sets the clock edge for data sampling.
0
1
Invert Receive Data
This bit enables inversion of receive data.
0
1
Unipolar Receive Data
This bit sets the port mode to dual-rail mode or unipolar mode.
0
1
A new frame search is started when 3 out of 8 contiguous F-bits
are in error.
A new frame search is started when 3 out of 16 contiguous F-bits
are in error.
Sample data on the rising edge of receive clock.
Sample data on the falling edge of receive clock.
Receive data is logic high (not inverted).
Receive data is logic low (inverted).
B3ZS (dual rail data input)
Unipolar mode (single rail data input)
278
Register Description
PEB 3456 E
05.2001
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