peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 100
peb3456
Manufacturer Part Number
peb3456
Description
Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456.pdf
(424 pages)
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4.7.3.4
A Pseudo-random bit sequence (PRBS) generator and monitor according to ITU O.151
can be activated for one particular logical channel. The PRBS pattern type can be
selected as 2
which should be used for PRBS can be defined in R/TPTSL register.
Additionally a fixed pattern can be programmed via registers R/TFPR0 and R/TFPR1
with length up to 32 bit to be defined in R/TPRBSC.FPL.
The PRBS monitor searches synchronization on the inverted and non-inverted PRBS
pattern. The current synchronization status is reported in status and interrupt status
registers. Each PRBS bit error will increment an error counter. An additional counter will
accumulate the total number of received bits. Synchronization will be reached within 400
ms with a probability of 99.9% and a BER of 1/10.
Recovery
The recovery procedure starts after detecting a logical ’1’ in the received bit stream. The
value via register PCR defines the number of pulses, which must occur during the time
interval 8*(PCD+1), to clear the LOS alarm.
4.7.3.3
The TE3-CHATT generates and detects a framed or unframed in-band loop up/actuate
(00001) and down/deactuate (001) pattern according to ANSI T1.403 with bit error rates
as high as 1/100. Replacing the transmit data with the in-band loop codes is done by
TCMDR.XLD / XLU for actuate or deactuate loop code.
The CPU must reset this bit to 0 for normal operation (no loop-back code). The TE3-
CHATT also offers the ability to generate and detect a flexible in-band loop up/actuate
and down/deactuate pattern. The loop up and down pattern is individual programmable
in the Loop Code Register from 5 to 8 bits in length.
Status and interrupt-status bits will inform the user whether Loop Up - or Loop Down
code was detected, but the CPU must activate the loop-back.
Data Sheet
In-Band Loop Generation and Detection
Pseudo-random Bit Sequence Generator and Monitor
15
-1 or 2
20
-1 via R/TPRBSC.PRP. Moreover, the number of the time slots
100
Functional Description
PEB 3456 E
05.2001
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