peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 191

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

ML/MG/IP/IL
Maximum Latency/Minimum Grant/Interrupt Pin/Interrupt Line
Access
Address
Reset Value
ML
MG
IP
IL
Data Sheet
31
15
: read/write
: 3C
: 06020100
Maximum Latency
This value specifies how often the device needs to access the PCI bus
in multiples of 1/4 us. The value is hardwired to 06
Minimum Grant
This value specifies how long of a burst period the device needs,
assuming a clock rate of 33 MHz in multiples of 1/4 us. The value is
hardwired to 02
Interrupt Pin
The interrupt pin register tells which interrupt pin the device uses. Refer
to section 6.2.4 and to section 2.2.6 of the PCI specification Rev. 2.1.
The value is hardwired to 01
Interrupt Line
The interrupt line register is used to communicate interrupt line routing
information.
ML(7:0)
H
IP(7:0)
H
H
.
24
8
191
H
.
23
7
MG(7:0)
IL(7:0)
Register Description
H
.
PEB 3456 E
05.2001
16
0