peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 30

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
V3, AA4, AD7,
AE9
AF4
Pin No.
C/BE(3:0)
PAR
Symbol
Output (O)
Input (I)
t/s
t/s
30
Command/Byte Enable
During
transaction, C/BE(3:0) define the bus
command. During the data phase, C/
BE(3:0) are used as byte enable lines.
The byte enable lines are valid for the
entire data phase and determine which
byte lanes carry meaningful data. C/BE(0)
applies to byte 0 (LSB) and C/BE(3)
applies to byte 3 (MSB).
When the TE3-CHATT is bus master, C/
BE(3:0) are outputs.
When the TE3-CHATT is bus slave, C/
BE(3:0) are inputs.
C/BE(3:0) are tri-stated when the TE3-
CHATT is not involved in the current
transaction.
C/BE(3:0) are updated and sampled on
the rising edge of CLK.
Parity
PAR is even parity across AD(31:0) and
C/BE(3:0). PAR is stable and valid one
clock after the address phase. PAR has
the same timing as AD(31:0) but delayed
by one clock.
When the TE3-CHATT is Master, PAR is
output during address phase and write
data phases and input during read data
phase. When the TE3-CHATT is Slave,
PAR is output during read data phase and
input during write data phase.
PAR is tri-stated when the TE3-CHATT is
not involved in the current transaction.
Parity errors detected by the device are
indicated on PERR output.
PAR is updated and sampled on the rising
edge of CLK.
the
address
Function
Pin Description
phase
PEB 3456 E
05.2001
of
a