mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 89

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

10.5.6 USB Control Register 2 (UCR2)
MC68HC05JB4
REV 2
T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit
ENDADD — Endpoint Address Select
TX1E — Endpoint 1/Endpoint 2 Transmit Enable
FRESUM — Force Resume
TP1SIZ3-TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet Size
UCR2
$0037
This read/write bit determines which type of data packet (DATA0 or DATA1) will
be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.
Toggling of this bit must be controlled by software. Reset clears this bit.
This read/write bit specifies whether the data inside the registers
UE1D0-UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a
successful Endpoint 2 USB response to a hosts IN token are satisfied
(TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit
is configured for Endpoint 1, the USB responds with a NAK handshake packet.
This read/write bit enables a transmit to occur when the USB Host controller
sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint
enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set.
Software should set the TX1E bit when data is ready to be transmitted. It must
be cleared by software when no more data needs to be transmitted.
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake
to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit.
This read/write bit forces a resume state (“K” or non-idle state) onto the USB
data lines to initiate a remote wake-up. Software should control the timing of the
forced resume to be between 10ms and 15 ms. Setting this bit will not cause
the RESUMF bit to set.
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 1 or Endpoint 2. These bits are cleared by reset.
reset
1 = DATA1 Token active for next Endpoint 1/Endpoint 2 transmit
0 = DATA0 Token active for next Endpoint 1/Endpoint 2 transmit
1 = The data buffers are used for Endpoint 2
0 = The data buffers are used for Endpoint 1
1 = Data is ready to be sent.
0 = Data is not ready. Respond with NAK.
1 = Force data lines to “K” state
0 = Default
W
R
BIT 7
-
Freescale Semiconductor, Inc.
Figure 10-25. USB Control Register 2 (UCR2)
For More Information On This Product,
= Unimplemented
TX1STR
UNIVERSAL SERIAL BUS MODULE
BIT 6
0
-
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February 24, 1999
TX1ST
BIT 5
0
BIT 4
0
-
ENABLE2 ENABLE1
GENERAL RELEASE SPECIFICATION
BIT 3
0
BIT 2
0
STALL2
BIT 1
0
STALL1
BIT 0
0