mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 50

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

GENERAL RELEASE SPECIFICATION
7.3.1 Port-B Data Register
7.3.2 Port-B Data Direction Register
7.3.3 Port-B Pull-up Control Register
7.4
Enabling or disabling the SLOW edge function does not change the pin
configuration. Reading from an output pin will return the content of the data
register.
SLOWEA
SLOWEB
PORT-C
Port-C is a 6-bit bi-directional port. The port-C data register is at $0002 and the
data direction register (DDRC) is at $0006. Reset does not affect the data regis-
ters, but clears the data direction registers, thereby returning the port pins to
inputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode.
When the ADON-bit is set, PC4 and PC5 are used as dedicated ADC reference
input, reference high (VRH) and reference low (VRL) respectively. And PC0 to
PC3 can be used as ADC inputs AD0 to AD3 when the appropriate channel is
PTB
$0001
DDRB
$0005
PURB
$0011
reset:
reset:
reset:
1 = Enable slow falling-edge output transition feature on PA6 and PA7.
0 = Disable slow falling-edge output transition feature on PA6 and PA7.
1 = Enable slow falling-edge output transition feature on PB0 to PB4.
0 = Disable slow falling-edge output transition feature on PB0 to PB4.
W
W
W
R
R
R
SLOWEA SLOWEB
BIT 7
BIT 7
BIT 7
0
0
0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
BIT 6
BIT 6
BIT 6
0
0
0
0
Go to: www.freescale.com
INPUT/OUTPUT PORTS
February 24, 1999
BIT 5
BIT 5
BIT 5
0
0
0
0
0
NOTE
DDRB4
PURB4
BIT 4
BIT 4
BIT 4
PB4
0
0
0
DDRB3
PURB3
BIT 3
BIT 3
BIT 3
PB3
0
0
0
DDRB2
PURB2
BIT 2
BIT 2
BIT 2
PB2
0
0
0
DDRB1
PURB1
BIT 1
BIT 1
BIT 1
PB1
0
0
0
DDRB0
PURB0
BIT 0
BIT 0
BIT 0
PB0
REV
0
0
0