mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 70

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

GENERAL RELEASE SPECIFICATION
10.2.1.1 Sync Pattern
The following sections will give some detail on each segment used to form a
complete USB transaction.
The NRZI (See Section 10.4.4.1) bit pattern shown in Figure 10-4 is used as a
synchronization pattern and is prefixed to each packet. This pattern is equivalent
to a data pattern of seven 0’s followed by a 1 (0x80).
The start of a packet (SOP) is signaled by the originating port by driving the D+
and D– lines from the idle state (also referred to as the “J” state) to the opposite
logic level (also referred to as the “K” state). This switch in levels represents the
first bit of the Sync field. Figure 10-5 shows the data signaling and voltage levels
for the start of packet and the sync pattern.
NRZI Data
Encoding
Handshake Packet:
Token Packet:
Data Packet:
SETUP
DATA0
DATA1
STALL
OUT
ACK
NAK
IN
Figure 10-3. Supported USB Packet Types
Freescale Semiconductor, Inc.
Idle
For More Information On This Product,
UNIVERSAL SERIAL BUS MODULE
Figure 10-4. Sync Pattern
Go to: www.freescale.com
SYNC
SYNC
SYNC
February 24, 1999
PID
PID
PID
SYNC PATTERN
PID
PID
PID
ADDR
EOP
0 - 8 bytes
DATA
ENDP
PID0 PID1
CRC5
CRC5
EOP
EOP
REV