mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 73

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

10.2.1.6 End Of Packet (EOP)
MC68HC05JB4
REV 2
Output
Data Stream
CRC16 Transmitted
MSB first after final
data byte.
Input / Output
Data Stream
The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The
single-ended 0 state is indicated by both D+ and D– being below 0.8 V. EOP will
be signaled by driving D+ and D– to the single-ended 0 state for two bit times
followed by driving the lines to the idle state for one bit time. The transition from
the single-ended 0 to the idle state defines the end of the packet. The idle state is
asserted for one bit time and then both the D+ and D– output drivers are placed in
their high-impedance state. The bus termination resistors hold the bus in the idle
state. Figure 10-8 shows the data signaling and voltage levels for an end of
packet transaction.
TRANSMIT
next bit
Figure 10-7. CRC Block Diagram for Data Packets
- Update every bit time
- Reset to ones at SOP
Freescale Semiconductor, Inc.
For More Information On This Product,
UNIVERSAL SERIAL BUS MODULE
Go to: www.freescale.com
RECEIVE
February 24, 1999
Good CRC
0
16
MUX
16
16
1
1 0 0 0 0
Generator Polynomial:
Y
GENERAL RELEASE SPECIFICATION
Equal?
0 0 0 0 0
0
1 0 0 0 0
16
N
0 0 0 1 0 1
Expected Residual:
0 0 0 0 0
Bad CRC
16
0 0 1 1 0 1