mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 36

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

GENERAL RELEASE SPECIFICATION
4.5.3 IRQ Control/Status Register (ICSR) - $0A
IRQ2
The IRQ interrupt function is controlled by the ICSR located at $000A. All unused
bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is
set by reset.
IRQR — IRQ Interrupt Acknowledge
IRQF — IRQ Interrupt Request Flag
ICSR
$000A
The IRQR acknowledge bit clears an IRQ interrupt by clearing the IRQ latch.
The IRQR acknowledge bit will always read as a logic zero.
Writing to the IRQF flag bit will have no effect on it. If the additional setting of
IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit
remains set the CPU will re-enter the IRQ interrupt sequence continuously until
either the IRQF flag bit or the IRQE enable bit is clear. The IRQF latch is
cleared by reset.
reset:
1 = Writing a logic one to the IRQR acknowledge bit will clear the IRQ
0 = Writing a logic zero to the IRQR acknowledge bit will have no effect
1 = Indicates that an IRQ request is pending.
0 = Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
W
R
latch.
on the IRQ latch.
pending. The IRQF flag bit can be cleared by writing a logic one to
the IRQR acknowledge bit to clear the IRQ latch and also
conditioning the external IRQ sources to be inactive (if the level
sensitive interrupts are enabled via mask option). Doing so before
exiting the service routine will mask out additional occurrences of
the IRQF.
IRQE
BIT 7
Figure 4-5. IRQ Control and Status Register (ICSR)
Figure 4-4. External Interrupt (IRQ2) Logic
1
Freescale Semiconductor, Inc.
For More Information On This Product,
IRQ2E
BIT 6
0
Go to: www.freescale.com
February 24, 1999
V
BIT 5
DD
INTERRUPTS
0
0
LATCH
IRQ2
R
BIT 4
0
0
ICSR ($0A)
IRQ2E
IRQ2R
BIT 3
IRQF
0
IRQ2F
BIT 2
0
IRQR
BIT 1
IRQ2
INTERRUPT
0
0
IRQ2R
BIT 0
REV
0
0