mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 65

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

9.6
MC68HC05JB4
REV 2
IEDG - INPUT CAPTURE EDGE SELECT
TIMER STATUS REGISTER (TSR)
The timer status register (TSR) shown in Figure 9-11 contains flags for the follow-
ing events:
Writing to any of the bits in the TSR has no effect. Reset does not change the
state of any of the flag bits in the TSR.
ICF - INPUT CAPTURE FLAG
OCF - OUTPUT COMPARE FLAG
TOF - TIMER OVERFLOW FLAG
TSR
$0013
U = UNAFFECTED BY RESET
The state of this read/write bit determines whether a positive or negative transi-
tion on the ICAP1 pin triggers a transfer of the contents of the timer register to
the input capture register. Reset has no effect on the IEDG bit.
•
•
•
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PB0/ICAP1 pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture
registers. Reset has no effect on ICF.
The OCF bit is automatically set when the value of the timer registers matches
the contents of the output compare registers. Clear the OCF bit by reading the
timer status register with the OCF set, and then accessing the low byte (OCRL,
$0017) of the output compare registers. Reset has no effect on OCF.
The TOF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the TOF bit by reading the timer status register with the
TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.
Reset has no effect on TOF.
reset:
1 = Positive edge (low to high transition) triggers input capture.
0 = Negative edge (high to low transition) triggers input capture.
An active signal on the PB0/ICAP1 pin, transferring the contents of the
timer registers to the input capture registers.
A match between the 16-bit counter and the output compare registers
An overflow of the timer registers from $FFFF to $0000.
W
R
BIT 7
ICF
U
Freescale Semiconductor, Inc.
Figure 9-11. Timer Status Registers (TSR)
For More Information On This Product,
BIT 6
OCF
U
Go to: www.freescale.com
February 24, 1999
BIT 5
TOF
16-BIT TIMER
U
BIT 4
0
0
GENERAL RELEASE SPECIFICATION
BIT 3
0
0
BIT 2
0
0
BIT 1
0
0
BIT 0
0
0