mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 63

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC05JB4
REV 2
OCRH
RESET
R/W
Writing to the OCRH before writing to the OCRL inhibits timer compares until the
OCRL is written. Reading or writing to the OCRL after reading the TSR will clear
the output compare flag bit (OCF).
To prevent OCF from being set between the time it is read and the time the output
compare registers are updated, use the following procedure:
OCRH
$0016
OCRL
$0017
U = UNAFFECTED BY RESET
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also
5. Enable interrupts by clearing the I bit in the condition code register
reset:
reset:
($FFFC)
clears the OCF flag bit in the TSR.
$0012
W
W
R
R
TIMER CONTROL REG.
Figure 9-8. Timer Output Compare Block Diagram
Figure 9-9. Output Compare Registers (OCRH, OCRL)
OCRH7
OCRL7
BIT 7
U
U
Freescale Semiconductor, Inc.
OCRH ($0016)
For More Information On This Product,
OCRH6
OCRL6
16-BIT COMPARATOR
BIT 6
16-BIT COUNTER
U
U
Go to: www.freescale.com
February 24, 1999
OCRH5
OCRL5
BIT 5
16-BIT TIMER
OUTPUT COMPARE
(OCF)
U
U
OCRL ($0017)
TIMER STATUS REG.
OCRH4
OCRL4
BIT 4
U
U
OCRH3
OCRL3
GENERAL RELEASE SPECIFICATION
BIT 3
$0013
U
U
OCRH2
OCRL2
BIT 2
U
U
4
OCRH1
OCRL1
BIT 1
U
U
INTERRUPT
OCRL
INTERNAL
REQUEST
INTERNAL
R/W
(f
CLOCK
TIMER
OSC
OCRH0
DATA
OCRL0
BUS
BIT 0
U
U
2)