mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 281

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable Bit
SPTIE— SPI Transmit Interrupt Enable Bit
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle
state and begin driving the MISO pin with the MSB of its data, once
the transmission begins, no new data is allowed into the shift register
from the data register. Therefore, the slave data register must be
loaded with the desired transmit data before the falling edge of SS.
Any data written after the falling edge is stored in the data register and
transferred to the shift register at the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. The same applies when SS is high for
a slave. The MISO pin is held in a high-impedance state, and the
incoming SPSCK is ignored. In certain cases, it may also cause the
MODF flag to be set. See
SS pin does not in any way affect the state of the SPI state machine.
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. See
SPE bit.
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
Serial Peripheral Interface Module (SPI)
13.7.2 Mode Fault
13.9 Resetting the
Serial Peripheral Interface Module (SPI)
Error. A logic 1 on the
SPI. Reset clears the
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