mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 241

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

12.4.4.3 PWM Initialization
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
NOTE:
To ensure correct operation when generating unbuffered or buffered
PWM signals, use this initialization procedure:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable
0 percent duty cycle generation and removes the ability of the channel
to self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
(TBSC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
1. In the TIMB status and control register (TBSC):
2. In the TIMB counter modulo registers (TBMODH–TBMODL), write
3. In the TIMB channel x registers (TBCHxH–TBCHxL), write the
4. In TIMB channel x status and control register (TBSCx):
5. In the TIMB status control register (TBSC), clear the TIMB stop bit,
the value for the required PWM period.
value for the required pulse width.
TSTOP.
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter by setting the TIMB reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB–MSxA. (See
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See
Timer Interface B (TIMB)
Table
Timer Interface B (TIMB)
Table
Advance Information
12-2.)
12-2.)
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