mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 24

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

List of Figures
Advance Information
24
Figure
11-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
11-2 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 206
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 212
11-4 TIMA Status and Control Register (TASC) . . . . . . . . . . . . . . . 218
11-5 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . 221
11-6 TIMA Counter Modulo Registers
11-7 TIMA Channel Status and Control Registers
11-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
11-9 TIMA Channel Registers (TACH0H/L–TACH3H/L) . . . . . . . . 228
12-1 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
12-2 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 234
12-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 238
12-4 TIMB Status and Control Register (TBSC) . . . . . . . . . . . . . . . 244
12-5 TIMB Counter Registers (TBCNTH and TBCNTL) . . . . . . . . . 247
12-6 TIMB Counter Modulo Registers
12-7 TIMB Channel Status and Control Registers
12-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
12-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . . . . 254
13-1 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .258
13-2 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .259
13-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 260
13-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 263
13-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
13-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 265
13-7 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 266
13-8 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .268
13-9 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 269
13-10 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 272
13-11 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 274
13-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
(TAMODH and TAMODL) . . . . . . . . . . . . . . . . . . . . . . . . . 222
(TASC0–TASC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
(TBMODH and TBMODL) . . . . . . . . . . . . . . . . . . . . . . . . . 248
(TBSC0–TBSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
List of Figures
Title
MC68HC908MR24
MOTOROLA
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Rev. 4.0
Page