mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 123

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.5.8 CGM CPU Interrupt (CGMINT)
8.6 CGM Registers
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
Notes:
$005C
$005D
$005E
Addr.
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL Bandwidth Control Register
PLL Programming Register
Register Name
PLL Control Register
See page 124.
See page 126.
See page 128.
programmable to be either the oscillator output, CGMXCLK, divided by
two or the VCO clock, CGMVCLK, divided by two.
CGMINT is the interrupt signal generated by the PLL lock detector.
These registers control and monitor operation of the CGM:
Figure 8-4
(PBWC)
•
•
•
(PCTL)
Figure 8-4. CGM I/O Register Summary
(PPG)
PLL control register (PCTL)
See
PLL bandwidth control register (PBWC)
See
PLL programming register (PPG)
See
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Clock Generator Module (CGM)
8.6.1 PLL Control
8.6.2 PLL Bandwidth Control
8.6.3 PLL Programming
is a summary of the CGM registers.
PLLIE
AUTO
MUL7
Bit 7
R
0
0
0
= Reserved
LOCK
MUL6
PLLF
R
R
6
0
0
1
PLLON
MUL5
ACQ
Register.
5
1
0
1
Register.
MUL4
BCS
XLD
0
0
0
4
Register.
VRS7
Clock Generator Module (CGM)
R
R
3
1
1
0
0
0
VRS6
R
R
2
1
1
0
0
1
Advance Information
VRS5
R
R
1
1
1
0
0
1
VRS4
Bit 0
R
R
1
1
0
0
0
123