mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 103

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mc68hc908mr24

Manufacturer Part Number
mc68hc908mr24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
7.6.1.1 Hardware Interrupts
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
I BIT
R/W
IDB
IAB
INTERRUPT
MODULE
SP – 4
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first.
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the load-accumulator-from-
memory (LDA) instruction is executed.
CCR
SP – 3
Figure 7-9. Interrupt Recovery
System Integration Module (SIM)
A
SP – 2
X
SP – 1
PC – 1[7:0]
SP
PC – 1[15:8]
PC
OPCODE
System Integration Module (SIM)
PC + 1
OPERAND
Advance Information
Figure 7-10
103

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