mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 227

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

11.8.5 TIMA Channel Registers
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
CHxMAX — Channel x Maximum Duty Cycle Bit
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB:MSxA 0:0), writing to the high byte of
the TIMA channel x registers (TACHxH) inhibits output compares until
the low byte (TACHxL) is written.
PTEx/TCHx
CHxMAX
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100 percent. As
Figure 11-8
is set or cleared. Also, TOVx bit takes effect in the cycle in which it is
set or cleared. The output stays at the 100 percent duty cycle level
until the cycle after CHxMAX is cleared.
TOVx
OVERFLOW
Timer Interface A (TIMA)
COMPARE
shows, the CHxMAX bit takes effect in the cycle after it
PERIOD
OUTPUT
Figure 11-8. CHxMAX Latency
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
Timer Interface A (TIMA)
Advance Information
COMPARE
OUTPUT
OVERFLOW
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