mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 271

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

13.8 Interrupts
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
NOTE:
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by clearing the SPE bit of the slave.
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then
write to the SPCR register. This entire clearing procedure must occur
with no MODF condition existing or else the flag is not cleared.
Four SPI status flags can be enabled to generate CPU interrupt requests
as shown in
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, provided that the SPI is
enabled (SPE = 1). (See
SPTE transmitter empty
SPRF receiver full
OVRF overflow
MODF mode fault
Serial Peripheral Interface Module (SPI)
Flag
Table
13-2.
SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver CPU interrupt request (SPRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
Table 13-2. SPI Interrupts
Figure
13-10.)
Serial Peripheral Interface Module (SPI)
Request
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