ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 49

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
October 2007
Region0
8 LRIO clock
Region1
8 LRIO clock
Region2
8 LRIO clock
Region3
8 LRIO clock
Table 2–15. Available Clocking Connections for Transceivers in 2SGX130G
Region
Global
Clock
v
v
v
v
Clock Resource
.
Other Transceiver Features
Other important features of the Stratix II GX transceivers are the power
down and reset capabilities, external voltage reference and bias circuitry,
and hot swapping.
Calibration Block
The Stratix II GX device uses the calibration block to calibrate the on-chip
termination for the PLLs and their associated output buffers and the
terminating resistors on the transceivers. The calibration block counters
the effects of process, voltage, and temperature (PVT). The calibration
block references a derived voltage across an external reference resistor to
calibrate the on-chip termination resistors on the Stratix II GX device. The
calibration block can be powered down. However, powering down the
calibration block during operations may yield transmit and receive data
errors.
Dynamic Reconfiguration
This feature allows you to dynamically reconfigure the PMA portion and
the channel parameters, such as data rate and functional mode, of the
Stratix II GX transceiver. The PMA reconfiguration allows you to quickly
optimize the settings for the transceiver’s PMA to achieve the intended
bit error rate (BER).
RCLK 20-27
RCLK 20-27
RCLK 12-19
RCLK 12-19
Regional
Clock
8 Clock I/O
Bank 13
v
8 Clock I/O
Bank 14
v
Stratix II GX Device Handbook, Volume 1
Transceiver
8 clock I/O
Bank 15
v
Stratix II GX Architecture
8 Clock I/O
Bank 16
v
v
2–41
8 Clock I/O
Bank 17
v