ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 114
ep2sgx30c
Manufacturer Part Number
ep2sgx30c
Description
Stratix Ii Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP2SGX30C.pdf
(314 pages)
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PLLs and Clock Networks
2–106
Stratix II GX Device Handbook, Volume 1
Clock pins
CLK12p
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
Enhanced PLL5 outputs
c0
c1
Table 2–28. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
(Part 1 of 2)
Regional Clock Network
Top Side Global and
Connectivity
The connections to the global and regional clocks from the top clock pins
and enhanced PLL outputs are shown in
the clocks from the bottom clock pins are shown in
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Table
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2–28. The connections to
Table
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Altera Corporation
2–29.
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October 2007
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