ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 304

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

JTAG Timing Specifications
JTAG Timing
Specifications
Figure 4–14. Stratix II GX JTAG Waveforms.
4–134
Stratix II GX Device Handbook, Volume 1
Captured
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
t
JCH
Figure 4–14
t
Notes to
(1)
(2)
(3)
t
JPZX
JSZX
Table 4–116. DQS Phase Offset Delay Per Stage (ps)
t
JCP
The delay settings are linear.
The valid settings for phase offset are -32 to +31.
The typical value equals the average of the minimum and maximum values.
t
Speed Grade
JSSU
t
JCL
Table
-3
-4
-5
shows the timing requirements for the JTAG signals
4–116:
t
JSH
t
t
JPCO
JSCO
t
JPSU
Min
10
10
10
Positive Offset
t
t
JSXZ
JPH
Max
15
15
16
t
JPXZ
Min
Negative Offset
Notes
8
8
8
Altera Corporation
(1), (2),
October 2007
Max
11
11
12
(3)