ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 302

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

External Memory Interface Specifications
External
Memory
Interface
Specifications
4–132
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
f
f
t
f
t
t
t
t
OUT_EXT
OUTDUTY
CONFIGPLL
CLBW
LOCK
PLL_PSERR
ARESET
ARESET_RECONFIG
Table 4–111. Fast PLL Specifications (Part 2 of 2)
This is limited by the I/O f
Name
Table
4–111:
PLL clock output frequency to regular I/O
Duty cycle for external clock output
Time required to reconfigure scan chains for
fast PLLs
PLL closed-loop bandwidth
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
Accuracy of PLL phase shift
Minimum pulse width on
Minimum pulse width on the
when using PLL reconfiguration. Reset the
PLL after
Tables 4–112
the dedicated circuitry used for interfacing with external memory
devices.
MAX
scandone
Table 4–112. DLL Frequency Range Specifications
Frequency Mode
. See
Description
Tables 4–91
0
1
2
3
goes high.
through
areset
through
areset
200 to 310 (–4 and –5 speed grade)
240 to 350 (–4 and –5 speed grade)
4–116
signal.
200 to 350 (–3 speed grade)
240 to 400 (–3 speed grade)
4–95
Frequency Range (MHz)
signal
contain Stratix II GX device specifications for
for the maximum.
100 to 175
150 to 230
4.6875
1.16
Min
500
45
10
75/f
0.03
SCANCLK
Typ
50
5
Altera Corporation
Max
±30
(1)
Resolution
55
28
(Degrees)
1
October 2007
22.5
30
30
30
36
36
MHz
MHz
Unit
ms
ns
ps
ns
ns
%