ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 106
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ep2sgx30c
Manufacturer Part Number
ep2sgx30c
Description
Stratix Ii Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP2SGX30C.pdf
(314 pages)
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PLLs and Clock Networks
2–98
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
EP2SGX30
EP2SGX60
EP2SGX90
EP2SGX130
Table 2–25. Stratix II GX Device PLL Availability
Device
EP2SGX30C/D and EP2SGX60C/D devices only have two fast PLLs (1 and 2), but the connectivity from these two
PLLs to the global and regional clock networks remains the same as shown. The EP2S60C/D devices only have
two enhanced PLLs (5 and 6).
The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic
before driving the fast PLL.
PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices. However, these PLLs are listed in
the Stratix II GX PLL numbering scheme is consistent with Stratix and Stratix II devices.
Table
2–25:
v
v
v
v
1
v
v
v
v
2
The Quartus II software enables the PLLs and their features without
requiring any external devices.
each Stratix II GX device and their type.
3
(3)
4
(3)
Fast PLLs
v
v
v
7
v
v
v
8
Notes
9
(1),
(3)
Table 2–25
(2)
10
(3)
shows the PLLs available for
v
v
v
v
5
Enhanced PLLs
v
v
v
v
6
Altera Corporation
Table 2–25
v
v
v
11
October 2007
because
12
v
v
v
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