ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 296
ep2sgx30c
Manufacturer Part Number
ep2sgx30c
Description
Stratix Ii Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP2SGX30C.pdf
(314 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ep2sgx30cF780C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
ep2sgx30cF780C5
Manufacturer:
ALTERA
Quantity:
672
Part Number:
ep2sgx30cF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
ep2sgx30cF780I4N
Manufacturer:
SANYO
Quantity:
10
- Current page: 296 of 314
- Download datasheet (4Mb)
High-Speed I/O Specifications
High-Speed I/O
Specifications
4–126
Stratix II GX Device Handbook, Volume 1
t
f
J
W
t
t
Timing unit interval (TUI)
f
f
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter
Output jitter
t
t
C
H S C L K
R I S E
F A L L
IN
H S D R
H S D R D P A
DUTY
L O C K
Table 4–106. High-Speed Timing Specifications and Definitions
High-Speed Timing Specifications
Table 4–106
1.2-V HSTL
LVPECL
Column DDIO Output I/O
Table 4–105. Maximum DCD for DDIO Output on Column I/O Pins With PLL in
the Clock Path (Part 2 of 2)
Maximum DCD (ps) for
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Fast PLL input clock frequency
Maximum/minimum LVDS data transfer rate (f
Maximum/minimum LVDS data transfer rate (f
The timing difference between the fastest and the slowest output edges
including t
same fast PLL. The clock is included in the TCCS measurement.
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Standard
provides high-speed timing specifications definitions.
CO
variation and clock skew across channels driven by the
Stratix-II Devices (PLL Output Feeding
C
/w).
-3 Device
180
155
Definitions
DDIO)
-4 and -5 Device
H S D R
H S D R D PA
180
= 1/TUI), non-DPA.
155
Altera Corporation
= 1/TUI), DPA.
October 2007
Unit
ps
ps
Related parts for ep2sgx30c
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: