ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 218
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ep2sgx30c
Manufacturer Part Number
ep2sgx30c
Description
Stratix Ii Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP2SGX30C.pdf
(314 pages)
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Operating Conditions
4–48
Stratix II GX Device Handbook, Volume 1
Note to
(1)
V
V
V
V
ΔV
V
ΔV
V
R
R
V
V
V
V
V
R
Table 4–31. 3.3-V PCML Specifications
Table 4–32. LVPECL Specifications
Symbol
CCIO
ID
ICM
OD
O C M
T
CCIO
ID
ICM
OD
OCM
1
2
L
Symbol
OD
O C M
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
(1)
Table
I/O supply voltage
Input differential voltage
swing (single-ended)
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode
voltage
Receiver differential input
resistor
4–32:
I/O supply voltage
Input differential voltage
swing (single-ended)
Input common mode
voltage
Output differential voltage
(single-ended)
Change in V
high and low
Output common mode
voltage
Change in V
high and low
Output termination voltage
Output external pull-up
resistors
Output external pull-up
resistors
Parameter
Parameter
O D
O C M
between
between
R
R
L
L
= 100 Ω
= 100 Ω
Conditions
Conditions
Minimum
Minimum
3.135
1,650
300
525
1.0
3.135
90
300
300
1.5
2.5
45
45
Typical
V
Typical
2.85
370
C C I O
3.3
50
50
600
100
3.3
Maximum
Altera Corporation
3.465
3.465
Maximum
600
500
3.3
50
50
55
55
CCINT
3.465
1,000
2,250
970
110
2.5
October 2007
, not V
Units
mV
mV
mV
mV
CCIO
V
V
V
V
Ω
Ω
Unit
mV
mV
mV
V
V
Ω
.
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