ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 102
ep2sgx30c
Manufacturer Part Number
ep2sgx30c
Description
Stratix Ii Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP2SGX30C.pdf
(314 pages)
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PLLs and Clock Networks
Figure 2–66. EP2SGX60, EP2SGX90 and EP2SGX130 Device I/O Clock Groups
2–94
Stratix II GX Device Handbook, Volume 1
IO_CLKM[7..0]
IO_CLKO[7..0]
IO_CLKN[7..0]
IO_CLKP[7..0]
8
8
8
8
IO_CLKA[7..0]
8
IO_CLKL[7..0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
IO_CLKB[7..0]
8
IO_CLKK[7..0]
8
IO_CLKC[7..0]
8
IO_CLKJ[7..0]
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
IO_CLKD[7..0]
8
IO_CLKI[7..0]
8
Altera Corporation
8
8
8
8
October 2007
IO_CLKE[7..0]
IO_CLKF[7..0]
IO_CLKG[7..0]
IO_CLKH[7..0]
I/O Clock Regions
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