pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 61

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

PM1 Event Registers (Status and Enable registers)
00h
01h
02h
03h
PM1 Control Registers
00h
01h
PM TImer Registers
00h
01h
02h
03h
General Purpose Event Registers
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h-
0Bh
0Ch
0Dh-
0Fh
Offset
The Power Management events are user-controlled via the
PM1 Event Registers: the enable bits in these registers give
the user the ability to tailor system response by enabling or
disabling Power Management options, and monitoring them
via the status bits. (e.g. Power Button, Real-Time Clock
Alarm or Wake State enabling or monitoring).
The PM Control registers enable control of system opera-
tion options (such as Power Button or Real-TIme CLock en-
abling, or reading Power Button override status).
The Power Management Timer registers house the values
of the Power Management Timer, which enables elapsed-
time detection for power-state control.
The General Purpose Event registers give the user control
over the General Purpose Power Management events: the
enable bits in these registers give the user the ability to tai-
lor system response by enabling or disabling the events
PM1_STS_LOW PM 1 Status Low Byte Register
PM1_STS_HIGH PM 1 Status High Byte Register
PM1_EN_LOW
PM1_EN_HIGH
PM1_CNT_LOW PM 1 Control Low Byte Register
PM1_CNT_HIGH PM 1 Control High Byte Register
PM1_TMR_LOW PM Timer Low Byte Register
PM1_TMR_MID
PM1_TMR_HIGH PM Timer High Byte Register
PM1_TMR_EXT PM Timer Extended Byte Register
GP1_STS0
GP1_STS1
GP1_STS2
GP1_STS3
GP1_EN0
GP1_EN1
GP1_EN2
GP1_EN3
GP2_EN0
Reserved
SMI_CMD
Reserved
TABLE 4-5. ACPI Fixed Register List.
Mnemonic
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
PM 1 Enable Low Byte Register
PM 1 Enable High Byte Register
PM Timer Middle Byte Register
General Purpose 1 Status 0 Reg.
General Purpose 1 Status 1 Reg.
General Purpose 1 Status 2 Reg.
General Purpose 1 Status 3 Reg.
General Purpose 1 Enable 0 Reg.
General Purpose 1 Enable 1 Reg.
General Purpose 1 Enable 2 Reg.
General Purpose 1 Enable 3 Reg.
General Purpose 2 Enable 0 Reg.
SMI Command Register
Description
61
from triggering interrupt requests, and monitoring them via
the status bits.
The Offsets indicated in the ACPI Fixed Register list are the
address offset values to be added to the Base Address val-
ues, to obtain the real addresses of the registers. The Base
Addresses are user-defined, at the following locations:
PM1 Event Registers (Status and Enable registers) base
address is located at the PM1 Event Base Address Bits 7-0
register and PM1 Event Base Address Bits 15-8 register of
the Power Management device (Logical Device 8).
PM1 Control Registers base address is located at the PM1
Control Base Address Bits 7-0 register and PM1 Control
Base Address Bits 15-8 register of the Power Management
device (Logical Device 8)
PM TImer Registers base address is located at the PM
Timer Base Address Bits 7-0 register and PM Timer Base
Address Bits 15-8 register of the Power Management de-
vice (Logical Device 8)
General Purpose Event Registers base address is locat-
ed at the General Purpose Status Base Address Bits 7-0
register and General Purpose Status Base Address Bits 15-
8 register of the Power Management device (Logical Device
8)
User Selectable Parameters
The APC function allows tailoring the system response to
power up, power down, power failure and battery operation
and other events.
User-selectable parameters include:
4.3.1
The system power state may be one of: No Power, Power
On, Power Off (suspended) or Power Failure. These states
are illustrated in FIGURE 4-11 "APC State Diagram" on
page 64. TABLE 4-6 "System Power States" on page 62 in-
dicates the power-source combinations for each state. No
other power-source combinations are valid.
In addition, the power sources and distribution for the entire
PC system are described in FIGURE 4-2 "PC87317VUL
Power Supplies" on page 55.
WARNING:
Enabling various external events to wake up the sys-
tem. See Section 4.4.2 "Entering Power States" on
page 65.
Wake-up time for an automatic system wake-up. See
“Predetermined Wake-Up” on page 68.
Type of system recovery after a Power Failure state.
See “The MOAP Bit” on page 62 and APCR6 bit 6 and
7 in “Bits 7,6 - Extended Wakeup options after Power
Failure.” on page 76.
Immediate or delayed Switch Off shutdown. See “The
SWITCH Input Signal” on page 67.
5 or 21 second time-out fail-safe shutdown. See “The
SWITCH Input Signal” on page 67.
LED signal response.
Mechanism for recognizing system power states. See
Section 4.3.2 "System Power Switching Logic" on
page 62.
Trigger characteristics for General Purpose events.
It is illegal for V
System Power States
DD
to be present when V
CCH
www.national.com
is absent.