pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 175

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bit 6 - Transmitter Empty (TXEMP)
Bit 7 - Error in RX_FIFO (ER_INF)
7.11.9 Modem Status Register (MSR)
The function of this register depends on the selected oper-
ational mode. When a UART mode is selected, this register
provides the current-state as well as state-change informa-
tion of the status lines from the modem or data transmission
module.
When any of the infrared modes is selected, the register
function is controlled by the setting of the IRMSSL bit in the
IRCR2 (see page 183). If IRMSSL is 0, the MSR register
works as in UART mode. If IRMSSL is 1, the MSR register
returns the value 30 hex, regardless of the state of the mo-
dem input lines.
When loopback is enabled, the MSR register works similar-
ly except that its status input signals are internally driven by
appropriate bits in the MCR register since the modem input
lines are internally disconnected. Refer to bits 3-0 at the
MCR (see page 172) and to the LOOP & ETDLBK bits at the
EXCR1 (see page 178) for more information.
A description of the various bits of the MSR register, with
Loopback disabled and UART Mode selected, is provided
below.
When bits 0, 1, 2 or 3 is set to 1, a Modem Status Event
(MS_EV) is generated if the MS_IE bit is enabled in the IER
Bits 0 to 3 are set to 0 as a result of any of the following
events:
In the reset state, bits 4 through 7 are indeterminate as they
reflect their corresponding input signals.
Note: The modem status lines can be used as general
It is cleared when a data character is written to the TXD
register.
This bit is set to 1 when the Transmitter Holding Regis-
ter or the TX_FIFO is empty, and the transmitter front-
end is idle.
In UART, Sharp-IR and SIR modes, this bit is set to a 1
if there is at least 1 framing error, parity error or break
indication in the RX_FIFO.
This bit is always 0 in the 16450 mode.
This bit is cleared upon read.
A hardware reset occurs.
The operational mode is changed and the IRMSSL bit
is 0.
The MSR register is read.
purpose inputs. They have no effect on the trans-
mitter or receiver operation.
Enhanced Serial Port with IR - UART2 (Logical Device 5)
175
Bit 0 - Delta Clear to Send (DCTS)
Bit 1 - Delta Data Set Ready (DDSR)
Bit 2 - Trailing Edge Ring Indicate (TERI)
Bit 3 - Delta Data Carrier Detect (DDCD)
Bit 4 - Clear To Send (CTS)
Bit 5 - Data Set Ready (DSR)
Bit 6 - Ring Indicate (RI)
Bit 7 - Data Carrier Detect (DCD)
7.11.10 Scratchpad Register (SPR)
This register shares a common address with the ASCR
Register.
In Non-Extended mode, this is a scratch register (as in the
16550) for temporary data storage.
X
7
Set to 1, when the CTS input signal changes state.
This bit is cleared upon read.
Set to 1, when the DSR input signal changes state.
This bit is cleared upon read
Set to 1, when the RI input signal changes state from
low to high.
This bit is cleared upon read
Set to 1, when the DCD input signal changes state.
1: DCD signal state changed.
This bit returns the inverse of the CTS input signal.
This bit returns the inverse of the DSR input signal.
This bit returns the inverse of the RI input signal.
This bit returns the inverse of the DCD input signal.
DCD
X
6
RI
FIGURE 7-16. MSR Register Bitmap
X
5
DSR
X
4
CTS
0
3
DDCD
0
2
TERI
0
1
DDSR
0
0
Reset
Required
DCTS
Register (MSR)
Modem Status
Offset 06h
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Bank 0,