pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 183

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

7.16 BANK 5 – INFRARED CONTROL REGISTERS
7.16.1 Reserved Registers
Bank 5 registers with offsets 00h-02h are reserved.
7.16.2 (LCR/BSR) Register
These registers are the same as the registers at offset 03h
in bank 0.
7.16.3 Infrared Control Register 2 (IRCR2)
This register controls the basic settings of the infrared
modes.
Upon reset, the content of this register is 02h.
Bit 0 - Enable Infrared Full Duplex Mode (IR_FDPLX)
Bit 1 - MSR Register Function Select in Infrared Mode
(IRMSSL)
05h - 07h
00-02h
Offset
0
0
7
03h
04h
When set to 1, the infrared receiver is not masked dur-
ing transmission.
This bit selects the behavior of the Modem Status Reg-
ister (MSR) and the Modem Status Interrupt (MS_EV)
when any infrared mode is selected. When a UART
mode is selected, the Modem Status Register and the
Modem Status Interrupt function normally, and this bit is
ignored.
0: MSR register and modem status interrupt work in
1: The MSR returns 30h, and the Modem Status In-
0
6
the IR modes as in the UART mode (Enables exter-
nal circuitry to perform carrier detection and pro-
vide wake-up events).
terrupt is disabled. (Default)
FIGURE 7-32. IRCR2 Register Bitmap
0
5
Reserved
Register
TABLE 7-20. Bank 5 Registers
IRCR2
0
Name
4
LCR/
BSR
AUX_IRRX
0
3
0
2
Link Control Register/
Bank Select Register
Infrared Control Register 2
Reserved
1
1
0
IRMSSL
0
Reserved
Reserved
Reset
Required
Enhanced Serial Port with IR - UART2 (Logical Device 5)
IR_FDPLX
Description
Infrared Control
Offset 04h
Register 2
(IRCR2)
Bank 5,
183
Bits 3,2 -Reserved
Bit 4 - Auxiliary Infrared Input Select (AUX_IRRX)
Bit 5-7 - Reserved
7.16.4 Reserved Registers
Bank 5 registers with offsets 05h-07h are reserved.
7.17 BANK 6 – INFRARED PHYSICAL LAYER
This Bank of registers controls aspects of the framing and
timing of the infrared modes.
7.17.1 Infrared Control Register 3 (IRCR3)
This Register enables/disables modulation in Sharp-IR
mode.
Upon reset, the content of this register is 20h.
Bit 0-5 - Reserved
04h - 07h
0
7
Offset
Read/Write 0.
When set to 1, the infrared signal is received from the
auxiliary input. (Separate input signals may be desired
for different front-end circuits). See Table 7-29 on page
190.
Read/Write 0.
Read/Write 0.
00h
01h
02h
03h
CONFIGURATION REGISTERS
SHDM_DS
0
6
FIGURE 7-33. IRCR3 Register Bitmap
SHMD_DS
1
0
5
TABLE 7-21. Bank 6 Register Set
LCR/ BSR
Register
SIR_PW
0
0
4
IRCR3
Name
0
0
3
0
0
2
0
0
1
Reserved
Infrared Control Register 3
SIR Pulse Width Control
0
0
0
Link Control Register/
Bank Select Register
Reserved
Reserved
Reset
Required
( 115 Kbps)
Description
Infrared Control
Register 3
Offset 00h
www.national.com
(IRCR3)
Bank 6,