pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 52

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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3.5.1
The DBBOUT register transfers data from the keyboard
controller to the PC87317VUL. It is written to by the key-
board controller and read by the PC87317VUL for transfer
to the PC. The PC may be notified of the need to read data
from the KBC by an interrupt request or by polling the Out-
put Buffer Full (OBF) bit (bit 0 of the KBC STATUS register
described in Section 3.5.3 "The KBC STATUS Register").
3.5.2
The DBBIN register transfers data from the PC87317VUL
system to the keyboard controller. (This transaction is trans-
parent to the user, who should program the device as if di-
rect access to the registers were in effect.)
When data is received in this manner, an Input Buffer Full
(IBF) internal interrupt may be generated in the KBC, to deal
with this data. Alternatively, reception of data in this manner
can be detected by the KBC polling the Input Buffer Full bit
(IBF, bit 1 of the KBC STATUS register).
3.5.3
The STATUS register holds information regarding the sys-
tem interface status.The bitmap below shows the bit defini-
tion of this register. This register is controlled by the KBC
firmware and hardware, and is read-only for the system.
FIGURE 3-8. KBC STATUS Configuration Register Bit-
0
7
6
0
The KBC DBBOUT Register, Offset 60h,
Read Only
The KBC DBBIN Register, Offset 60h (F1 Clear)
or 64h (F1 Set), Write Only
The KBC STATUS Register
5
0
KBC CLK
4
0
General Purpose
3
0
Flags
2
0
F1 Command or Data Flag
1
0
F0 General Purpose Flag
map
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
0
0
IBF Input Buffer Full
Reset
S1
OBF Output Buffer Full
KBC Status Register
FIGURE 3-9. Instruction Timing
1 Instruction Cycle = 15 Clock Cycles
S2
Offset 64h
Read Only
S3
52
Bit 0 - OBF, Output Buffer Full
Bit 1 - IBF, Input Buffer Full
Bit 2 - F0, General Purpose Flag
Bit 3 - F1, Command/Data Flag
Bits 7-4, General Purpose Flags
3.6 INSTRUCTION TIMING
The KBC clock is first divided by 3 to generate the state tim-
ing, then by 5 to generate the instruction timing. Thus each
instruction cycle consists of five states and 15 clock cycles.
Most keyboard controller instructions require only one in-
struction cycle, while some require two cycles. Refer to the
8042 or PC87323VUL instruction set for details.
A 1 indicates that data has been written into the DB-
BOUT register by the KBC. It is cleared by a system
read operation from DBBOUT.
When a write operation is performed by the host system,
this bit is set to 1, which may be set up to trigger the IBF
interrupt. Upon executing an IN A, DBB instruction, it is
cleared.
A general purpose flag that can be cleared or toggled by
the keyboard controller firmware.
This flag holds the state of address line A2 while a write
operation is performed by the host system. It distin-
guishes between commands and data from the host
system. In this device, a write with A2 = 1 (hence F1 =
1) is defined as a command, and A2 = 0 (hence F1 = 0)
is data.
These flags may be modified by KBC firmware.
S4
S5
S1