pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 223

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bits 7-4 - Reserved
10.2.10 WATCHDOG Status Register (WDST)
Bit 1 of this register contains the value of the WDO signal,
for monitoring by software.
On reset or on PM logical device activation this register is
initialized to 01h.
See Section 10.1.2 "WATCHDOG Feature" on page 218 for
more information.
Bit 0 - WDO Value
Bits 7-1 - Reserved
10.2.11 PM1 Event Base Address Register (Bits 7-0)
This read/write register holds the base address bits 7-0 of
the PM1 Event Registers of the ACPI fixed registers (See
Logical device 2).
Bits 0,1 are read-only. On reset this register is initialized to
00h.
0
7
0: UART2 IRQ trigger disabled. (Default)
1: An active UART2 IRQ signal triggers reloading of
Reserved
This read-only bit reflects the value of WDO. It is initial-
ized to 1 by a hardware reset.
This bit reflects the status of the WDO signal, even if
WDO is not configured for output by bit 6 of SuperI/O
Configuration register 2, in which case the pin is used
for GPIO17.
0: WDO is active.
1: WDO is not active. (Default)
0
6
the WATCHDOG timer.
FIGURE 10-10. WDST Register Bitmap
0
5
0
4
0
3
Reserved
0
2
0
1
1
0
Reset
Required
WDO Value
WATCHDOG Status
Register (WDST)
Power Management (Logical Device 8)
Index 07h
223
10.2.12 PM1 Event Base Address Register (Bits 15-8)
This read/write register holds the base address bits 15-8 of
the PM1 Event Registers of the ACPI fixed registers (See
Logical device 2).
On reset this register is initialized to 00h.
10.2.13 PM Timer Base Address (Bits 7-0)
This read/write register holds the base address bits 7-0 of
the PM Timer Registers of the ACPI fixed registers (See
Logical device 2).
Bits 0,1 are read-only. On reset this register is initialized to
00h.
0
0
0
7
7
7
FIGURE 10-13. PM Timer Base Address Bits 7-0
FIGURE 10-12. PM1 Bits 15-8 Register Bitmap
FIGURE 10-11. PM1 Bits 7-0 Register Bitmap
0
0
0
6
6
6
0
0
0
5
5
5
0
0
0
4
4
4
0
0
0
3
3
3
PM1 Event Base Address Bits 7-0
PM1 Event Base Address Bits 15-8
PM TImer Base Address Bits 7-0
Register Bitmap
0
0
0
2
2
2
0
0
0
1
1
1
0
0
0
0
0
0
PM1 Event Base Address
PM1 Event Base Address
Reset
Required
Reset
Required
Reset
Required
PM Timer Base Address
Register Bits 15-8,
Register Bits 7-0,
Register Bits 7-0,
Index 0Ah
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Index 08h
Index 09h