pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 13
pc87317vul
Manufacturer Part Number
pc87317vul
Description
Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87317VUL.pdf
(272 pages)
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9.0
10.0
8.8
8.9
General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip
Select Output Signals
9.1
9.2
9.3
Power Management (Logical Device 8)
10.1
10.2
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
8.7.7
BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS .......................................... 210
8.8.1
8.8.2
8.8.3
8.8.4
UART1 REGISTER BITMAPS ................................................................................................. 211
GPIO PORT ACTIVATION ...................................................................................................... 215
GPIO CONTROL REGISTERS ............................................................................................... 215
9.2.1
9.2.2
9.2.3
9.2.4
PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS ......................................................... 216
POWER MANAGEMENT OPTIONS ....................................................................................... 218
10.1.1
10.1.2
POWER MANAGEMENT REGISTERS ................................................................................... 218
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
10.2.9
10.2.10 WATCHDOG Status Register (WDST) ...................................................................... 223
10.2.11 PM1 Event Base Address Register (Bits 7-0) ............................................................ 223
10.2.12 PM1 Event Base Address Register (Bits 15-8) .......................................................... 223
10.2.13 PM Timer Base Address (Bits 7-0) ............................................................................ 223
10.2.14 PM Timer Base Address Register (Bits 15-8) ............................................................ 224
10.2.15 PM1 Control Base Address Register (Bits 7-0) ......................................................... 224
10.2.16 PM1 Control Base Address Register (Bits 15-8) ....................................................... 224
10.2.17 General Purpose Status Base Address Register (Bits 7-0) ....................................... 224
10.2.18 General Purpose Status Base Address Register (Bits 15-8) ..................................... 224
Extended Control Register 1 (EXCR1) ...................................................................... 208
Line Control Register (LCR) and Bank Select Register (BSR) .................................. 209
Extended Control and Status Register 2 (EXCR2) .................................................... 209
Reserved Register ..................................................................................................... 209
TX_FIFO Current Level Register (TXFLV) ................................................................ 209
RX_FIFO Current Level Register (RXFLV) ............................................................... 210
Module Revision ID Register (MRID) ........................................................................ 210
Shadow of Line Control Register (SH_LCR) ............................................................. 210
Shadow of FIFO Control Register (SH_FCR) ............................................................ 211
Line Control Register (LCR) and Bank Select Register (BSR) .................................. 211
Special GPIO Signal Features ................................................................................... 215
Reading and Writing to GPIO Pins ............................................................................ 215
Multiplexed GPIO Signals .......................................................................................... 215
Multiplexed GPIO Signal Selection ............................................................................ 215
Configuration Options ................................................................................................ 218
WATCHDOG Feature ................................................................................................ 218
Power Management Index Register .......................................................................... 218
Power Management Data Register ........................................................................... 219
Function Enable Register 1 (FER1) ........................................................................... 219
Function Enable Register 2 (FER2) ........................................................................... 219
Power Management Control Register (PMC1) .......................................................... 220
Power Management Control 2 Register (PMC2) ....................................................... 221
Power Management Control 3 Register (PMC3) ....................................................... 221
WATCHDOG Time-Out Register (WDTO) ................................................................ 222
WATCHDOG Configuration Register (WDCF) .......................................................... 222
Table of Contents
13
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