pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 154

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Bit 2 - Paper End (PE) Internal Pull-up or Pull-down
Resistor Select
Bits 5- 3 - ECP IRQ Number
Bit 6 - Demand DMA Enable
Bit 7 - Bit 3 of CNFGA
on page 149. Actual ECP DMA routing is controlled by
the DMA channel select register (index 74h) of this log-
ical device.
Microsoft’s ECP protocol and ISA interface standard de-
fine bits 1 and 0 of CNFGB as shown in TABLE 6-7
"ECP Mode DMA Selection" on page 150.
0: PE has a nominal 25 K
1: PE has a nominal 25 K internal pull-up resistor.
These bits identify the ECP IRQ number, as reflected on
bits 5 through 3 of the ECP CNFGB register. See Sec-
tion 6.5.11 "Configuration Register B (CNFGB)" on
page 149. Actual ECP IRQ routing is controlled by inter-
rupt select register (index 70h) of this logical device.
Microsoft’s ECP protocol and ISA interface standard de-
fines bits 5 through 3 of CNFGB, as shown in TABLE
6-8 "ECP Mode Interrupt Selection" on page 150.
If enabled, DRQ is asserted when a FIFO threshold of 4
is reached or when flush-time-out expires, except when
DMA fairness prevents DRQ assertion. The threshold of
4 is for four empty entries forward and for four valid en-
tries backward.
Once DRQ is asserted, it is held asserted for four DMA
transfers, as long as the FIFO is able to process these
four transfers, i.e., FIFO not empty backward.
When these four transfers are done, the DRQ behaves
as follows:
— If DMA fairness prevents DRQ assertion (as in the
— If the FIFO is not able to process another four trans-
— If the FIFO is able to process another four transfers
The flush time-out is an 8-bit counter that counts 256
clocks of 24 MHz and triggers DRQ assertion when the
terminal-count is reached, i.e., when flush time-out ex-
pires). The counter is enabled for counting backward
when the peripheral state machine writes a byte and
DRQ is not asserted. Once enabled, it counts the 24
MHz clocks. The counter is reset and disabled when
DRQ is asserted. The counter is also reset and disabled
for counting forward and when demand the DMA is dis-
abled.
This mechanism is reset whenever ECP mode is
changed, the same way the FIFO is flushed in this case.
0: Disabled.
1: Enabled.
This bit may be utilized by the user. The value of this bit
is reflected on bit 3 of the ECP CNFGA register.
tor.
case of 32 consecutive DMA transfers) then DRQ
becomes low.
fers (below threshold), then DRQ is becomes low.
(still above the threshold and no fairness to prevent
DRQ assertion), then DRQ is held asserted as de-
tailed above.
internal pull-down resis-
Parallel Port (Logical Device 4)
154
6.6 DETAILED ECP MODE DESCRIPTIONS
TABLE 6-11 "ECP Modes" on page 155 summarizes the
functionality of the ECP in each mode. The following Sec-
tions describe how the ECP functions in each mode, in de-
tail.
6.6.1
Software controlled data transfer is supported in modes 000
and 001. The software generates peripheral-device cycles
by modifying the DATAR and DCR registers and reading
the DSR, DCR and DATAR registers. The negotiation
phase and nibble mode transfer, as defined in the IEEE
1284 standard, are performed in these modes.
In these modes the FIFO is reset (empty) and is not func-
tional, the DMA and RLE are idle.
Mode 000 is for the forward direction only; the direction bit
(bit 5 of DCR) is forced to 0 and PD7-0 are driven. Mode 001
is for both the forward and backward directions. The direc-
tion bit controls whether or not pins PD7-0 are driven.
6.6.2
Automatic data transfer (ECP cycles generated by hard-
ware) is supported only in modes 010 and 011 (Parallel Port
and ECP FIFO modes). Automatic DMA access to fill or
empty the FIFO is supported in modes 010, 011 and 110.
Mode 010 is for the forward direction only; the direction bit
is forced to 0 and PD7-0 are driven. Mode 011 is for both
the forward and backward directions. The direction bit con-
trols whether PD7-0 are driven.
Automatic Run Length Expanding (RLE) is supported in the
backward direction.
Forward Direction (Bit 5 of DCR = 0)
When the ECP is in forward direction and the FIFO is not full
(bit 1 of ECR is 0) the FIFO can be filled by software writes
to the FIFO registers (AFIFO and DFIFO in mode 011, and
CFIFO in mode 010).
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to fill the
FIFO with data bytes (not including command bytes).
When the ECP is in forward direction and the FIFO is not
empty (bit 0 of ECR is 0) the ECP pops a byte from the FIFO
and issues a write signal to the peripheral device. The ECP
drives AFD according to the operation mode (bits 7-5 of
ECR) and according to the tag of the popped byte as fol-
lows:
ECP (Forward) Write Cycle
An ECP write cycle starts when the ECP drives the popped
tag onto AFD and the popped byte onto PD7-0. When
BUSY is low the ECP asserts STB. In 010 mode the ECP
deactivates STB to terminate the write cycle. In 011 mode
the ECP waits for BUSY to be high.
When BUSY is high, the ECP deactivates STB, and chang-
es AFD and PD7-0 only after BUSY is low.
In Parallel Port FIFO mode (mode 010) AFD is con-
trolled by bit 1 of DCR.
In ECP mode (mode 011) AFD is controlled by the
popped tag. AFD is driven high for normal data bytes
and driven low for command bytes.
Software Controlled Data Transfer
(Modes 000 and 001)
Automatic Data Transfer
(Modes 010 and 011)