pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 18

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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CFG1-0
CS0
CS2,1
CSOUT-
NSC-Test
CTS2,1
D7-0
DACK3-0
DCD2,1
DENSEL
DIR
DR1,0
DRATE0
Signal/Pin
Name
68
106
71
141, 131
10-3
59-56
142, 132
94
90
88, 87
84
144, 138 Configuration
72, 71
Number
Pin
NSC-use
Purpose
Purpose
ISA-Bus
ISA-Bus
Module
General
General
UART1,
UART1,
UART2
UART2
FDC
FDC
FDC
FDC
Group 21
Group 12
Group 21
Group 16
Group 16
Group 16
Group 20
Group #
Signal/Pin Connection and Description
Group 5
Group 9
Group 1
Group 8
Group 1
Group 1
I/O and
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
I/O
I/O
Configuration Strap Pins 1-0 – These pins determine the default
configuration upon power up. These pins are pulled down by internal
30 K
CFG1 is multiplexed with DTR2 and BOUT2. CFG0 is multiplexed with
SOUT1. See Table 2-2 on page 28.
Programmable Chip Select – CS0, CS1 and CS2 are programmable
chip select and/or latch enable and/or output enable signals that have
many uses, for example, as game ports or for I/O port expansion.
The decoded address and the assertion conditions are configured via
the chip configuration registers. See Section 2.3 on page 29.
CS0 is multiplexed with LED on pin 68 and with P12 on pin 106. On
pin 68 is an open-drain output that is in TRI-STATE unless V
applied.
CS1 is multiplexed with CSOUT-NSC-Test/XD0.
CS2 is multiplexed with XD1.
Chip Select Read Output, NSC-Test – National Semiconductor test
output. This is an open-drain output signal.
This signal is multiplexed with CS1 and XD0.
UART1 and UART2 Clear to Send – When low, these signals indicate
that the modem or other data transfer device is ready to exchange data.
CTS2 is multiplexed with GPIO30.
ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is
the LSB and D7 is the MSB. These signals have 24 mA (sink)
buffered outputs.
DMA Acknowledge 0,1,2 and 3 – These active low input signals
acknowledge a request for DMA services and enable the IOWR and
IORD input signals during a DMA transfer. These DMA signals can be
mapped to the following logical devices: FDC, UART1, UART2 or
parallel port.
UART1 and UART2 Data Carrier Detected – When low, this signal
indicates that the modem or other data transfer device has detected
the data carrier.
DCD2 is multiplexed with GPIO31
Density Select – Indicates that a high FDC density data rate (500
Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is
selected.
DENSELs polarity is controlled by bit 5 of the SuperI/O FDC
Configuration register as described in Section 2.6.1 on page 40.
Direction – This output signal determines the direction of the Floppy
Disk Drive (FDD) head movement (active = step in, inactive = step
out) during a seek operation. During reads or writes, DIR is inactive.
Drive Select 0 and 1 – These active low output signals are the
decoded drive select output signals. DR0 and DR1 are controlled by
Digital Output Register (DOR) bits 0 and 1. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is 1, as described in Section 2.6.1.
See MTR0,1 for more information.
Data Rate 0 – This output signal reflects the value of bit 0 of the
Configuration Control Register (CCR) or the Data Rate Select Register
(DSR), whichever was written to last. Output from the pin is totem-pole
buffered (6 mA sink, 6 mA source).
resistors. Use external 10 K
18
Function
pull-up resistors to V
DD
.
DD
is