pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 153

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bits 2-0 - Reserved
Bit 3 - EPP 1.7 ZWS Control
Bit 4 - EPP 1.7/1.9 Select
Bit 5 - Reserved
Bit 6 - Channel Address Enable
Bit 7 - SPP Compatibility
6.5.18 Control4 Register
Upon reset this register is initialized to 00000111.
This register enables control of the fairness mechanism of
the DMA by programming the maximum number of bus cy-
cles that the parallel port DMA request signals can remain
active, and the minimum number of clock cycles that they
will remain inactive after they were deactivated.
Upon reset this bit is initialized to 0. This bit controls as-
sertion of ZWS on EPP 1.7 access.
There is no ZWS assertion on SPP and on EPP 1.9 ac-
cess. ZWS is always asserted on ECP access.
Control of ZWS assertion on parallel port access, except
in EPP mode, is done via the SuperI/O Configuration 1
register. See Section 2.4.3 "SuperI/O Configuration 1
Register (SIOC1)" on page 37.
0: ZWS not asserted on EPP 1.7 access.
1: ZWS asserted on EPP 1.7 access.
Selects EPP version 1.7 or 1.9.
0: EPP version 1.7.
1: EPP version 1.9.
When this bit is 1, mode is 011, direction is backward,
there is an input command (BUSY is 0), and bit 7 of the
data is 1, the command is written into the FIFO.
See “Bits 7-5 - ECP Mode Control” on page 151 for a de-
scription of each mode.
0: Modes 000, 001 and 100 are identical to ECP.
1: Modes 000 and 001 of the ECP are identical with
Modes 000, 001 and 100 differ as follows:
000, 001 and 100 – Reading DCR returns pin values of
000 and 001 – Reading DCR returns 1 for bit 5.
000, or 001 or 100 when bit 5 of DCR is 0 (forward di-
000, 001, and 100, when bit 4 of DCR is 0 – IRQx is
001 – IRQx is a level interrupt generated on the trailing
Compatible and Extended modes of the SPP (see
Section 6.1 "PARALLEL PORT CONFIGURATION"
on page 137), and mode 100 of the ECP is com-
patible with EPP mode.
bits 3-0.
rection) – Reading DATAR returns register latched
value instead of pin values.
floated.
edge of ACK. Bit 2 of the DSR is the IRQ status bit
(same behavior as bit 2 of the STR).
Parallel Port (Logical Device 4)
153
Bits 2- 0 - Parallel Port DMA Request Active Time
Bit 3 - Reserved
Bits 6-4 - Parallel Port DMA Request Inactive Time
Bit 7 - Reserved
6.5.19 PP Confg0 Register
Upon reset this register is initialized to 00h.
Bits 1, 0 - ECP DMA Channel Number
0
7
0
7
This field specifies the maximum number of consecutive
bus cycles that the parallel port DMA signals can remain
active.
The default value is 111, which specifies 32 cycles.
When these bits are 0, the number is 1 cycle.
Otherwise, the number is 4(n+1) where n is the value of
these bits.
This field specifies the minimum number of clock cycles
that the parallel port DMA signals remain inactive after
being deactivated by the fairness mechanism.
The default value is 000, which specifies 8 clock cycles.
Otherwise, the number of clock cycles is 8 + 32n, where
n is the value of these bits.
These bits identify the ECP DMA channel number, as
reflected on bits 1 and 0 of the ECP CNFGB register.
See Section 6.5.11 "Configuration Register B (CNFGB)"
Reserved
Bit 3 of CNFGA
0
6
0
6
FIGURE 6-33. PP Confg0 Register Bitmap
FIGURE 6-32. Control4 Register Bitmap
Demand DMA Enable
0
5
0
5
0
PP DMA Request Inactive Time
4
0
4
0
3
ECP IRQ Number
0
3
Reserved
1
2
0
2
1
PE Internal Pull-up or Pull-down
1
0
1
1
0
PP DMA Request
Active Time
0
0
ECP DMA Channel Number
Reset
Required
Reset
Required
PP Confg0 Register
Control4 Register
Second Level
Second Level
Offset 04h
Offset 05h
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