pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 50

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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3.3.4
The keyboard controller includes an 8-bit counter, which
can be used as a timer or an event counter, as selected by
the firmware.
Timer Operation
When the internal clock is chosen as the counter input, the
counter functions as a timer. The clock fed to the timer con-
sists of the KBC instruction cycle clock, divided by 32. (See
FIGURES 3-9 "Instruction Timing" on page 52 and 3-5
"Timing Generation and Timer Circuit".) The divisor is reset
only by a hardware reset or when the timer is started by an
STRT T instruction.
Event Counter Operation
When the clock input of the counter is switched to the exter-
nal input (MCLK), it becomes an event counter. The falling
edge of the signal on the MCLK pin causes the counter to
increment. Timer Overflow Flag and Timer interrupt operate
as in the timer mode.
3.4 EXTERNAL I/O INTERFACES
The PC chip set interfaces with the PC87317VUL as illus-
trated in FIGURE 3-2 "System Interfaces" on page 48.
All data transactions between the KBC and the PC chip set
are handled by the PC87317VUL.
The PC87317VUL decodes all I/O device chip-select func-
tions from the address bus. The KBC chip-select codes are,
traditionally, 60h or 64h, as described in TABLE 3-1 "Sys-
tem Interface Operations" on page 51. (These addresses
are user-programmable.)
The external interface includes two sets of signals: the key-
board and mouse interface signals, and the general-pur-
pose I/O signals.
External
24 or 48 MHz
Clock
External
32768 Hz
Crystal
Timer or Event Counter
(MCLK)
X1C
X2C
X1
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
Frequency
Multiplier
(1465)
FIGURE 3-5. Timing Generation and Timer Circuit
TEST1
Counter
3-State
Counter
5-Cycle
48 MHz
External Event Input
Source
Prescaler
Select
Clock
Timer
32-Bit
50
3.4.1
Four serial I/O signals interface with the external keyboard
and mouse. These signals are driven by open-collector driv-
ers with signals derived from two I/O ports residing on the
internal bus. Each output can drive 16 mA, making them
suitable for driving the keyboard and mouse cables. The
signals are named KBCLK, KBDAT, MCLK and MDAT, and
they are the logical complements of P26, P27, P23 and
P22, respectively.
TEST0 and TEST1 are dedicated test pins, internally con-
nected to KBCLK and MCLK, respectively, as shown in FIG-
URES 3-1 "KBC System Functional Block Diagram" on
page 47 and 3-2 "System Interfaces" on page 48. These
pins may be used as logical conditions for conditional jump
instructions, which directly check the logical levels at the
pins.
KBDAT and MDAT are connected to pins P10 and P11, re-
spectively.
MCLK also provides input to the event counter.
When the KBC is disabled, the KBCLK, KBDAT, MCLK and
MDAT pins can be put in TRI-STATE. The KBC can be dis-
abled via the Activate register in logical device 0 or via bit 0
of FER1 register in logical device 8. The above pins can be
put in TRI-STATE via bit 0 of the SuperI/O KBC Configura-
tion register in logical device 0 or via bit 0 of the PMC1 reg-
ister in logical device 8. The Activate register in logical
device 1 has no effect on these pins.
3.4.2
The P12, P16, P17, P20 and P21 general purpose I/O sig-
nals interface to two I/O ports (port1 and port2). P12, P16
and P17 are mapped to port 1 and P20 and P21 are
mapped to port 2.
P12 port’s output can be routed internally to POR and/or
SCI. (See Section 4.4.3 "System Power-Up and Power-Off
Activation Event Description" on page 67)
KBC Clock
Timer
Keyboard and Mouse Interface
General Purpose I/O Signals
Stop
2
Counter
Frequency
8-Bit Timer
or Counter
Select
Interrupt
2 or 3
Overflow
Flag