pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 133

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bits 3-0 - Delay Before Processing Factor
Execution Phase
Internal registers are written.
Result Phase
None.
5.7.22 The VERIFY Command
The VERIFY command verifies the contents of data and/or
address fields after they have been formatted or written.
VERIFY reads logical sectors containing a normal data Ad-
dress Mark (AM) from the selected drive, without transfer-
ring the data to the host.
The TC signal cannot terminate this command since no
data is transferred. Instead, VERIFY simulates a TC signal
by setting the Enable Count (EC) bit to1. In this case, VER-
IFY terminates when the number of sectors read equals the
number of sectors to read, i.e., Sectors to read Count (SC).
If SC = 0 then 256 sectors will be verified.
When EC is 0, VERIFY ends when the End of the Track
(EOT) sector number equals the number of the sector
checked. In this case, the ninth command phase byte is not
needed and should be set to FFh.
TABLE 5-27 "VERIFY Command Termination Conditions"
on page 134 shows how different values for the VERIFY pa-
rameters affect termination.
These bits specify a factor that is multiplied by a con-
stant to determine the delay before command process-
ing starts, i.e., from selection of a drive motor until a
read or write operation starts.
The value of the Motor Timer Values (TMR) bit (bit 7) of
the second command phase byte in the MODE com-
mand determines which group of constants and delay
ranges to use. See “Bit 7 - Motor Timer Values (TMR)”
on page 119.
The specific constant that will be multiplied by this factor
to determine the actual delay before processing for
each data transfer rate shown in TABLE 5-25 "Constant
Multipliers for Delay Before Processing Factor and De-
lay Ranges".
Use the smallest possible value for this factor, except 0,
i.e., 1. If this factor is 0, the value128 is used.
133
Command Phase
First Command Phase Byte
Second Command Phase Byte
Bits 2-0 - Drive Select (DS1,0) and Head (HD) Select
Bit 7 - Enable Count Control (EC)
Third through Eighth Command Phase Bytes
Ninth Command Phase Byte, Sectors to Read Count (SC)
MT
EC
7
See Section 5.7.10 "The READ DATA Command" on
page 122 for a description of these bits.
See the description of the Drive Select bits (DS1,0) and
the Head (HD) in Section 5.7.10 "The READ DATA
Command" on page 122.
This bit controls whether the End of Track sector num-
ber or the Sectors to read Count (SC) triggers termina-
tion of the VERIFY command.
See also TABLE 5-27 "VERIFY Command Termination
Conditions".
0: Terminate VERIFY when the number of last sector
1: Terminate VERIFY when number of sectors read
See Section 5.7.10 "The READ DATA Command" on
page 122.
Always set the End of Track (EOT) sector number to the
number of the last sector to be checked on each side of
the disk. If EOT is greater than the number of sectors
per side, the command terminates with an error and no
useful Address Mark (AM) or CRC data is returned.
This byte specifies the number of sectors to read. If the
Enable Count (EC) control bit (bit 7) of the second com-
mand byte is 0, this byte is not needed and should be
set to the value FFh.
read equals the End of Track (EOT) sector number.
The ninth command phase byte (Sectors to read
Count, SC), is not needed and should be set to FFh.
equals the number of sectors to read, i.e., Sectors
to read Count (SC).
MFM
X
6
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Sectors to read Count (SC)
SK
X
5
Bytes-Per-Sector Code
Sector Number
Track Number
Head Number
X
4
1
X
3
0
HD
2
1
DS1
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1
1
DS0
0
0