LM3S102-IRN20 Luminary Micro, Inc., LM3S102-IRN20 Datasheet - Page 7

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LM3S102-IRN20

Manufacturer Part Number
LM3S102-IRN20
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
List of Figures
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10. MICROWIRE Frame Format (Single Frame)........................................................................... 236
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................................... 237
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 238
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. Master Burst RECEIVE ........................................................................................................... 270
Figure 13-11. Master Burst RECEIVE after Burst SEND............................................................................... 271
October 6, 2006
Stellaris High-Level Block Diagram ........................................................................................... 23
LM3S102 Controller System-Level Block Diagram ................................................................... 29
CPU Block Diagram .................................................................................................................. 31
TPIU Block Diagram .................................................................................................................. 32
JTAG Module Block Diagram .................................................................................................... 39
Test Access Port State Machine ............................................................................................... 42
IDCODE Register Format.......................................................................................................... 46
BYPASS Register Format ......................................................................................................... 46
Boundary Scan Register Format ............................................................................................... 47
External Circuitry to Extend Reset............................................................................................. 49
Main Clock Tree ........................................................................................................................ 52
Flash Block Diagram ................................................................................................................. 86
GPIO Module Block Diagram .................................................................................................. 101
GPIO Port Block Diagram........................................................................................................ 102
GPIODATA Write Example...................................................................................................... 103
GPIODATA Read Example ..................................................................................................... 103
GPTM Module Block Diagram ................................................................................................. 139
16-Bit Input Edge Count Mode Example ................................................................................. 143
16-Bit Input Edge Time Mode Example................................................................................... 144
16-Bit PWM Mode Example .................................................................................................... 145
WDT Module Block Diagram ................................................................................................... 170
UART Module Block Diagram.................................................................................................. 194
UART Character Frame........................................................................................................... 195
SSI Module Block Diagram...................................................................................................... 229
TI Synchronous Serial Frame Format (Single Transfer).......................................................... 231
TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 232
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 233
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 233
Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 234
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 234
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 235
Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 235
I
I
Data Validity During Bit Transfer on the I
START and STOP Conditions ................................................................................................. 265
Complete Data Transfer with a 7-Bit Address ......................................................................... 266
R/S Bit in First Byte ................................................................................................................. 267
Master Single SEND................................................................................................................ 267
Master Single RECEIVE.......................................................................................................... 268
Master Burst SEND ................................................................................................................. 269
2
2
C Block Diagram ................................................................................................................... 264
C Bus Configuration.............................................................................................................. 265
Preliminary
2
C Bus..................................................................... 265
LM3S102 Data Sheet
7

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