LM3S102-IRN20 Luminary Micro, Inc., LM3S102-IRN20 Datasheet - Page 48
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LM3S102-IRN20
Manufacturer Part Number
LM3S102-IRN20
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S102-IRN20.pdf
(335 pages)
- Current page: 48 of 335
- Download datasheet (2Mb)
System Control
6
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
48
System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
Functional Description
The System Control module provides the following capabilities:
Device Identification
Seven read-only registers provide software with information on the microcontroller, such as
version, part number, SRAM size, Flash size, and other features. See the DID0, DID1 and
DC0-DC4 registers starting on page 56.
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
Reset Sources
The controller has six sources of reset:
1.
2.
3.
4.
5.
6.
After a reset, the Reset Cause (RESC) register (see page 73) is set with the reset cause. The bits
in this register are sticky and maintain their state across multiple reset sequences, except when an
external reset is the cause, and then all the other bits in the RESC register are cleared.
Note:
RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals
except the JTAG TAP controller (see “JTAG Interface” on page 38). The external reset sequence is
as follows:
1.
2.
Device identification, see page 48
Local control, such as reset (see page 48), power (see page 51) and clock control (see
page 51)
System control (Run, Sleep, and Deep-Sleep modes), see page 53
External reset input pin (RST) assertion, see page 48.
Power-on reset (POR), see page 49.
Internal brown-out (BOR) detector, see page 49.
Software-initiated reset (with the software reset registers), see page 50.
A watchdog timer reset condition violation, see page 50.
Internal low drop-out (LDO) regulator output, see page 51.
The external reset pin (RST) is asserted and then de-asserted.
After RST is de-assserted, the main crystal oscillator must be allowed to settle and there is an
internal main oscillator counter that takes from 15-30 ms to account for this. During this time,
internal reset to the rest of the controller is held active.
The main oscillator is used for external resets and power-on resets; the internal oscillator
is used during the internal process by internal reset and clock verification circuitry.
Preliminary
October 6, 2006
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