LM3S102-IRN20 Luminary Micro, Inc., LM3S102-IRN20 Datasheet - Page 148
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LM3S102-IRN20
Manufacturer Part Number
LM3S102-IRN20
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S102-IRN20.pdf
(335 pages)
- Current page: 148 of 335
- Download datasheet (2Mb)
General-Purpose Timers
9.4
Table 9-2. GPTM Register Map
148
Offset
0x00C
0x01C
0x02C
0x03C
0x000
0x004
0x008
0x018
0x020
0x024
0x028
0x030
0x034
0x038
0x040
0x044
GPTMRIS
GPTMTBILR
GPTMTBPR
Name
GPTMCFG
GPTMTAMR
GPTMTBMR
GPTMCTL
GPTMIMR
GPTMMIS
GPTMICR
GPTMTAILR
GPTMTAMATCHR
GPTMTBMATCHR
GPTMTAPR
GPTMTAPMR
GPTMTBPMR
7.
8.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change
takes effect at the next cycle after the write.
Register Map
Table 9-1 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s
address, relative to that timer’s base address:
If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR)
register and the GPTM Timern Prescale Match (GPTMTnPMR) register.
Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
Timer0: 0x40030000
Timer1: 0x40031000
0x00000000
0x00000000
0x00000000
0x0000FFFF
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x0000FFFF
0x00000000
0x00000000
0x00000000
0x00000000
0x0000FFFF
0x0000FFFF
0xFFFFFFFF
0xFFFFFFFF
Reset
a
a
Preliminary
Type
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Description
Configuration
TimerA mode
TimerB mode
Control
Interrupt mask
Interrupt status
Masked interrupt status
Interrupt clear
TimerA interval load
TimerB interval load
TimerA match
TimerB match
TimerA prescale
TimerB prescale
TimerA prescale match
TimerB prescale match
October 6, 2006
page
See
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