LM3S102-IRN20 Luminary Micro, Inc., LM3S102-IRN20 Datasheet - Page 290
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LM3S102-IRN20
Manufacturer Part Number
LM3S102-IRN20
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S102-IRN20.pdf
(335 pages)
- Current page: 290 of 335
- Download datasheet (2Mb)
Inter-Integrated Circuit (I2C) Interface
290
Write-Only Control Register
Bit/Field
31:1
0
0
reserved
RREQ
Name
DA
Type
WO
RO
RO
Reset
Preliminary
0
0
0
Description
Receive Request
This bit specifies the status of the I
to outstanding receive requests. If set, the I
outstanding receive data from the I
clock stretching to delay the master until the data has
been read from the I2CSDR register. Otherwise, no
receive data is outstanding.
Reserved bits return an indeterminate value, and should
never be changed.
Device Active
1=Enables the I
0=Disables the I
2
2
C slave operation.
C slave operation.
2
2
C slave with regards
C master and uses
October 6, 2006
2
C unit has
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