LM3S102-IRN20 Luminary Micro, Inc., LM3S102-IRN20 Datasheet - Page 205
![no-image](/images/no-image-200.jpg)
LM3S102-IRN20
Manufacturer Part Number
LM3S102-IRN20
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S102-IRN20.pdf
(335 pages)
- Current page: 205 of 335
- Download datasheet (2Mb)
October 6, 2006
Bit/Field
2:0
4
3
reserved
BUSY
Name
RXFE
Type
RO
RO
RO
Reset
1
0
0
Preliminary
Reserved bits return an indeterminate value, and should never
Description
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding
register is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is
empty.
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit
remains set until the complete byte, including all stop bits, has
been sent from the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
be changed.
LM3S102 Data Sheet
205
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